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Date:   Wed, 3 Apr 2019 20:04:08 -0500
From:   Rob Herring <robh@...nel.org>
To:     Borislav Petkov <bp@...en8.de>
Cc:     James Morse <james.morse@....com>,
        Yash Shah <yash.shah@...ive.com>,
        linux-riscv@...ts.infradead.org, linux-edac@...r.kernel.org,
        Palmer Dabbelt <palmer@...ive.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Mark Rutland <mark.rutland@....com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2
 cache Controller

On Fri, Mar 29, 2019 at 3:24 PM Borislav Petkov <bp@...en8.de> wrote:
>
> On Fri, Mar 29, 2019 at 02:41:05PM -0500, Rob Herring wrote:
> > DT dictates aligning with what the h/w looks like which has little to
> > do with OS driver design.
>
> Ok, then, where does this goal for doing a driver or compilation unit
> per IP block come from?
>
> Because everytime an ARM EDAC driver pops up, we are having the same
> discussion.
>
> > I never said you should change EDAC and I outlined how things should
> > be handled if it is one driver.
>
> Ok, we will add that to the EDAC driver design document we're currently
> working on.
>
> > DT and OS subsystems are independent things. I can't tell you how to
> > design the subsystem and you can't dictate DT design (based on EDAC
> > design).
>
> I don't think I've ever intentionally or unintentionally dictated DT
> design - all I've opposed to is having multiple EDAC drivers on ARM.

No, but folks just extend 1 driver to mean 1 DT node because that's
easy and certainly the more common case.

Rob

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