linux-kernel - Re: [LINUX PATCH v2 3/3] spi: spi-mem: Add support for Zynq QSPI controller

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Date:   Fri, 5 Apr 2019 11:45:23 +0530
From:   Vignesh Raghavendra <vigneshr@...com>
To:     Naga Sureshkumar Relli <nagasure@...inx.com>,
        "broonie@...nel.org" <broonie@...nel.org>,
        "bbrezillon@...nel.org" <bbrezillon@...nel.org>
CC:     "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
        "dwmw2@...radead.org" <dwmw2@...radead.org>,
        "marek.vasut@...il.com" <marek.vasut@...il.com>,
        "richard@....at" <richard@....at>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Michal Simek <michals@...inx.com>,
        "nagasuresh12@...il.com" <nagasuresh12@...il.com>
Subject: Re: [LINUX PATCH v2 3/3] spi: spi-mem: Add support for Zynq QSPI
 controller



On 05/04/19 10:55 AM, Naga Sureshkumar Relli wrote:
> Hi Vignesh,
> 
> Thanks for the review.
> 
>> -----Original Message-----
>> From: Vignesh Raghavendra <vigneshr@...com>
>> Sent: Friday, April 5, 2019 10:14 AM
>> To: Naga Sureshkumar Relli <nagasure@...inx.com>; broonie@...nel.org;
>> bbrezillon@...nel.org
>> Cc: linux-spi@...r.kernel.org; dwmw2@...radead.org; marek.vasut@...il.com;
>> richard@....at; linux-mtd@...ts.infradead.org; linux-kernel@...r.kernel.org; Michal Simek
>> <michals@...inx.com>; nagasuresh12@...il.com
>> Subject: Re: [LINUX PATCH v2 3/3] spi: spi-mem: Add support for Zynq QSPI controller
>>
>>
>>
>> On 01/04/19 1:29 PM, Naga Sureshkumar Relli wrote:
>>> +/**
>>> + * zynq_qspi_config_op - Configure QSPI controller for specified transfer
>>> + * @xqspi:	Pointer to the zynq_qspi structure
>>> + * @qspi:	Pointer to the spi_device structure
>>> + *
>>> + * Sets the operational mode of QSPI controller for the next QSPI
>>> +transfer and
>>> + * sets the requested clock frequency.
>>> + *
>>> + * Return:	0 on success and -EINVAL on invalid input parameter
>>> + *
>>> + * Note: If the requested frequency is not an exact match with what
>>> +can be
>>> + * obtained using the prescalar value, the driver sets the clock
>>> +frequency which
>>> + * is lower than the requested frequency (maximum lower) for the
>>> +transfer. If
>>> + * the requested frequency is higher or lower than that is supported
>>> +by the QSPI
>>> + * controller the driver will set the highest or lowest frequency
>>> +supported by
>>> + * controller.
>>> + */
>>> +static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct
>>> +spi_device *spi) {
>>> +	u32 config_reg, baud_rate_val = 0;
>>> +
>>> +	/*
>>> +	 * Set the clock frequency
>>> +	 * The baud rate divisor is not a direct mapping to the value written
>>> +	 * into the configuration register (config_reg[5:3])
>>> +	 * i.e. 000 - divide by 2
>>> +	 *      001 - divide by 4
>>> +	 *      ----------------
>>> +	 *      111 - divide by 256
>>> +	 */
>>> +	while ((baud_rate_val < ZYNQ_QSPI_BAUD_DIV_MAX)  &&
>>> +	       (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
>>> +		spi->max_speed_hz)
>>> +		baud_rate_val++;
>>> +
>>
>> Instead use DIV_ROUND_UP, something like below should work(untested):
>>
>> 	unsigned long refclk_rate = clk_get_rate(xqspi->refclk);
>> 	u32 baud_rate_val = DIV_ROUND_UP(refclk_rate, spi->max_speed_hz) - 1;
>>

Oops, sorry, I had meant

	u32 baud_rate_val = DIV_ROUND_UP(refclk_rate, 2 * spi->max_speed_hz) - 1;

But please ignore my comment, I see that div values goes by power of 2 and not multiple of 2

Regards
Vignesh

> This is not just direct calculation.
> i.e. for example
> refclk_rate = 200MHz and max_speed_hx = 100MHz.
> then DIV_ROUND_UP gives a value of 2.
> But writing a value of 2 to config registers means, divide by 8. But we should write divide by 2 (value of zero).
> That’s why we implemented the above calculation.
> 
> 000: divide by 2.
> 001: divide by 4
> 010: divide by 8
> 011: divide by 16
> 100: divide by 32
> 101: divide by 64
> 110: divide by 128
> 111: divide by 256
> 



-- 
Regards
Vignesh