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Message-ID: <1554423259-26056-12-git-send-email-skomatineni@nvidia.com>
Date: Thu, 4 Apr 2019 17:14:11 -0700
From: Sowjanya Komatineni <skomatineni@...dia.com>
To: <thierry.reding@...il.com>, <jonathanh@...dia.com>,
<talho@...dia.com>, <skomatineni@...dia.com>, <broonie@...nel.org>,
<robh+dt@...nel.org>, <mark.rutland@....com>,
<kyarlagadda@...dia.com>
CC: <ldewangan@...dia.com>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<devicetree@...r.kernel.org>
Subject: [PATCH V2 12/20] spi: tegra114: add support for LSBYTE_FIRST
Some SPI devices expects SPI transfers to be in Least significant byte
first order and some devices expect Most significant byte first order.
This patch adds SPI_LSBYTE_FIRST to the supported SPI mode list and also
configures Tegra SPI controller accordingly.
Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
---
drivers/spi/spi-tegra114.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 212bb90aa0cb..d3b95bba2361 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -755,6 +755,11 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
else
command1 &= ~SPI_LSBIT_FE;
+ if (spi->mode & SPI_LSBYTE_FIRST)
+ command1 |= SPI_LSBYTE_FE;
+ else
+ command1 &= ~SPI_LSBYTE_FE;
+
if (spi->mode & SPI_3WIRE)
command1 |= SPI_BIDIROE;
else
@@ -1164,7 +1169,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
- SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
+ SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE |
+ SPI_LSBYTE_FIRST;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
master->setup = tegra_spi_setup;
master->transfer_one_message = tegra_spi_transfer_one_message;
--
2.7.4
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