linux-kernel - [tip:perf/core] perf vendor events intel: Update Bonnell to V4

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Message-ID: <tip-b1580f542ca7d4bec387559b05e62b1b2f5f08d2@git.kernel.org>
Date:   Fri, 5 Apr 2019 05:02:16 -0700
From:   tip-bot for Andi Kleen <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, tglx@...utronix.de, hpa@...or.com,
        mingo@...nel.org, jolsa@...nel.org, acme@...hat.com,
        ak@...ux.intel.com, kan.liang@...el.com
Subject: [tip:perf/core] perf vendor events intel: Update Bonnell to V4

Commit-ID:  b1580f542ca7d4bec387559b05e62b1b2f5f08d2
Gitweb:     https://git.kernel.org/tip/b1580f542ca7d4bec387559b05e62b1b2f5f08d2
Author:     Andi Kleen <ak@...ux.intel.com>
AuthorDate: Thu, 14 Mar 2019 14:55:07 -0700
Committer:  Arnaldo Carvalho de Melo <acme@...hat.com>
CommitDate: Mon, 1 Apr 2019 15:23:42 -0300

perf vendor events intel: Update Bonnell to V4

Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Cc: Kan Liang <kan.liang@...el.com>
Cc: Jiri Olsa <jolsa@...nel.org>
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
 tools/perf/pmu-events/arch/x86/bonnell/frontend.json | 2 +-
 tools/perf/pmu-events/arch/x86/bonnell/pipeline.json | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
index 935b7dcf067d..ef69540ab61d 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
@@ -77,7 +77,7 @@
         "UMask": "0x1",
         "EventName": "UOPS.MS_CYCLES",
         "SampleAfterValue": "2000000",
-        "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ",
+        "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
         "CounterMask": "1"
     }
 ]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
index b2e681c78466..09c6de13de20 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
@@ -189,7 +189,7 @@
         "UMask": "0x8",
         "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
         "SampleAfterValue": "200000",
-        "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect. "
+        "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect."
     },
     {
         "EventCode": "0x89",