linux-kernel - Re: [PATCH v2 00/21] Remove Mysterious Macro Intended to Obscure Weird Behaviours (mmiowb())

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Message-ID: <20190405163027.GA19813@fuggles.cambridge.arm.com>
Date:   Fri, 5 Apr 2019 17:30:27 +0100
From:   Will Deacon <will.deacon@....com>
To:     Linus Torvalds <torvalds@...ux-foundation.org>
Cc:     linux-arch <linux-arch@...r.kernel.org>,
        Linux List Kernel Mailing <linux-kernel@...r.kernel.org>,
        "Paul E. McKenney" <paulmck@...ux.ibm.com>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Michael Ellerman <mpe@...erman.id.au>,
        Arnd Bergmann <arnd@...db.de>,
        Peter Zijlstra <peterz@...radead.org>,
        Andrea Parri <andrea.parri@...rulasolutions.com>,
        Palmer Dabbelt <palmer@...ive.com>,
        Daniel Lustig <dlustig@...dia.com>,
        David Howells <dhowells@...hat.com>,
        Alan Stern <stern@...land.harvard.edu>,
        "Maciej W. Rozycki" <macro@...ux-mips.org>,
        Paul Burton <paul.burton@...s.com>,
        Ingo Molnar <mingo@...nel.org>,
        Yoshinori Sato <ysato@...rs.sourceforge.jp>,
        Rich Felker <dalias@...c.org>, Tony Luck <tony.luck@...el.com>,
        Mikulas Patocka <mpatocka@...hat.com>,
        Akira Yokosawa <akiyks@...il.com>,
        Luis Chamberlain <mcgrof@...nel.org>,
        Nicholas Piggin <npiggin@...il.com>
Subject: Re: [PATCH v2 00/21] Remove Mysterious Macro Intended to Obscure
 Weird Behaviours (mmiowb())

On Fri, Apr 05, 2019 at 06:15:12AM -1000, Linus Torvalds wrote:
> On Fri, Apr 5, 2019 at 6:09 AM Will Deacon <will.deacon@....com> wrote:
> > >
> > > Or did I miss something? I think the ia64() mb/rmb/wmb stuff only
> > > works on normal memory on ia64.
> >
> > I was worried about RISC-V, but actually their wmb() is "fence ow,ow"
> > which I think is stronger than their mmiowb() "fence o,w" implementation.
> 
> Also with smp_store_release -> smp_load_acquire kind of ordering?

Hmm, to be honest, I'm not convinced that smp_load_acquire() is ordered
wrt subsequent I/O on RISC-V anyway, so in the pattern of:

CPU 0:
writel(1, dev);
wmb();
smp_store_release(&x, 1);

CPU 1:
if (smp_load_acquire(&x) == 1)
	writel(2, dev)

then I think it's actually the control dependency in CPU 1 that provides
the expected ordering. That's probably quite fragile.

> Again, this is not at all a NAK - I think we should do this - just
> perhaps a request to add a note to the commit and make people aware of
> the issue.

Right, I'll do that.

Will