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Message-ID: <20190405185902.GA15808@linux.intel.com>
Date: Fri, 5 Apr 2019 11:59:02 -0700
From: Sean Christopherson <sean.j.christopherson@...el.com>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: LKML <linux-kernel@...r.kernel.org>, x86@...nel.org,
Andy Lutomirski <luto@...nel.org>,
Josh Poimboeuf <jpoimboe@...hat.com>
Subject: Re: [patch V2 07/29] x86/exceptions: Make IST index zero based
On Fri, Apr 05, 2019 at 05:07:05PM +0200, Thomas Gleixner wrote:
> The defines for the exception stack (IST) array in the TSS are using the
> SDM convention IST1 - IST7. That causes all sorts of code to subtract 1 for
> array indices related to IST. That's confusing at best and does not provide
> any value.
>
> Make the indices zero based and fixup the usage sites. The only code which
> needs to adjust the 0 based index is the interrupt descriptor setup which
> needs to add 1 now.
>
> Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
> ---
Reviewed-by: Sean Christopherson <sean.j.christopherson@...el.com>
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