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Message-ID: <87bm1hz8lg.fsf@notabene.neil.brown.name>
Date: Mon, 08 Apr 2019 09:41:47 +1000
From: NeilBrown <neil@...wn.name>
To: George Hilliard <thirtythreeforty@...il.com>,
George Hilliard <thirtythreeforty@...il.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
devel@...verdev.osuosl.org, Nishad Kamdar <nishadkamdar@...il.com>,
linux-kernel@...r.kernel.org,
Sergej Perschin <ser.perschin@...il.com>,
Matthias Brugger <matthias.bgg@...il.com>,
John Crispin <blogic@...nwrt.org>
Subject: Re: [PATCH 03/16] staging: m57621-mmc: delete driver from the tree.
On Wed, Apr 03 2019, George Hilliard wrote:
> On Tue, Apr 2, 2019 at 3:45 PM Christian Lütke-Stetzkamp
> <christian@...mp.de> wrote:
>> There are two other larger differences that I found during my
>> work. One is that drivers/mmc/host/mtk-sd.c has much more features,
>> like voltage and clock handling and some support for high speed
>> modes. I don't know if these features are required/useful for this
>> device.
>
> For what it's worth, I found an old forum post of someone who was
> dealing with a crashy kernel on their mt7688. They removed the
> mt7621-mmc driver and hacked the clock code out of the mainline
> driver. Apparently it worked. I never got around to duplicating
> their work, however. (I too ran into severe instability problems with
> the mt7621-mmc driver, but they only appeared in conjunction with
> using the SLOB allocator. I could never debug it because when JTAG
> was turned on, the SDMC peripheral was disabled for some reason I
> never discovered. More info on that if someone is interested.)
>
> The correct way to do this would be to have a "compatible" flag that
> bypassed the clock handling code. I don't think there are any
> relevant clocks to set up on the MT7628/MT7688 - the MSDC peripheral
> does not appear in the clock plan.
>
>> The other thing is the card detect handling. This driver is
>> doing the card detect / read only detection on its own, where the in
>> tree one just uses some default gpio functions there and I don't know
>> weather this must be changed or weather there is a gpio driver for the
>> mt7621.
>
> There is a "mtk,mt7621-gpio"-compatible GPIO driver available.
> Probably it would work with GPIO on new hardware that did not to route
> CD to the CD pin, because the CD pin is muxed using the same "SD card"
> pin state as the SD data pins. I do not know if it is possible for
> the GPIO peripheral to read the pin while it is muxed to the SD
> controller, as would be necessary for existing hardware.
>
> George
FYI I have mmc working on my mt7621 board using the
drivers/mmc/host/mtk_sd.c driver and the following patch.
I haven't looked at the card-detect yet.
I'll post bits of this to relevant lists as they are ready, not to this
list any more. If anyone would like to hear about my progress, please
let me know.
Thanks,
NeilBrown
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 833ef0590af8..45ae93114a07 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -366,6 +366,8 @@ struct mtk_mmc_compatible {
u8 clk_div_bits;
bool hs400_tune; /* only used for MT8173 */
u32 pad_tune_reg;
+ u32 caps;
+ u32 ocr_avail;
bool async_fifo;
bool data_tune;
bool busy_check;
@@ -507,6 +509,21 @@ static const struct mtk_mmc_compatible mt7622_compat = {
.support_64g = false,
};
+static const struct mtk_mmc_compatible mt7620_compat = {
+ .clk_div_bits = 8,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE,
+ .async_fifo = false,
+ .data_tune = false,
+ .busy_check = false,
+ .stop_clk_fix = false,
+ .enhance_rx = false,
+ .caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED |
+ MMC_CAP_SD_HIGHSPEED),
+ .ocr_avail = (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 |
+ MMC_VDD_31_32 | MMC_VDD_32_33),
+};
+
static const struct of_device_id msdc_of_ids[] = {
{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
@@ -514,6 +531,7 @@ static const struct of_device_id msdc_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
+ { .compatible = "ralink,mt7620-sdhci", .data = &mt7620_compat},
{}
};
MODULE_DEVICE_TABLE(of, msdc_of_ids);
@@ -2194,13 +2212,17 @@ static int msdc_drv_probe(struct platform_device *pdev)
if (mmc->caps & MMC_CAP_SDIO_IRQ)
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
- mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
+ mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23 |
+ host->dev_comp->caps;
+ mmc->f_max = host->src_clk_freq;
/* MMC core transfer sizes tunable parameters */
mmc->max_segs = MAX_BD_NUM;
mmc->max_seg_size = BDMA_DESC_BUFLEN;
mmc->max_blk_size = 2048;
mmc->max_req_size = 512 * 1024;
mmc->max_blk_count = mmc->max_req_size / 512;
+ mmc->ocr_avail |= host->dev_comp->ocr_avail;
+
if (host->dev_comp->support_64g)
host->dma_mask = DMA_BIT_MASK(36);
else
@@ -2226,8 +2248,13 @@ static int msdc_drv_probe(struct platform_device *pdev)
msdc_ungate_clock(host);
msdc_init_hw(host);
- ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
- IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
+ if (irq_get_trigger_type(host->irq) == IRQ_TYPE_NONE)
+ ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ pdev->name, host);
+ else
+ ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
+ 0, pdev->name, host);
if (ret)
goto release;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 86f630045c13..54f33857a17d 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -34,6 +34,12 @@
clock-output-names = "cpu", "bus";
};
+ mmc_clock: mmc_clock@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ };
+
palmbus: palmbus@...00000 {
compatible = "palmbus";
reg = <0x1E000000 0x100000>;
@@ -292,6 +298,13 @@
compatible = "ralink,mt7620-sdhci";
reg = <0x1E130000 0x4000>;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&sdhci_pins>;
+ pinctrl-1 = <&sdhci_pins>;
+
+ clocks = <&mmc_clock &mmc_clock>;
+ clock-names = "source", "hclk";
+
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
};
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