linux-kernel - Re: [PATCH V5 08/12] perf/x86/intel: Add Icelake support

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Message-ID: <20190408150654.GV12232@hirez.programming.kicks-ass.net>
Date:   Mon, 8 Apr 2019 17:06:54 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     kan.liang@...ux.intel.com
Cc:     acme@...nel.org, mingo@...hat.com, linux-kernel@...r.kernel.org,
        tglx@...utronix.de, jolsa@...nel.org, eranian@...gle.com,
        alexander.shishkin@...ux.intel.com, ak@...ux.intel.com
Subject: Re: [PATCH V5 08/12] perf/x86/intel: Add Icelake support

On Tue, Apr 02, 2019 at 12:45:05PM -0700, kan.liang@...ux.intel.com wrote:
> +static struct event_constraint *
> +icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> +			  struct perf_event *event)
> +{
> +	/*
> +	 * Fixed counter 0 has less skid.
> +	 * Force instruction:ppp in Fixed counter 0
> +	 */
> +	if ((event->attr.precise_ip == 3) &&
> +	    ((event->hw.config & X86_RAW_EVENT_MASK) == 0x00c0))
> +		return &fixed_counter0_constraint;

Does that want to be:

		event->hw.config == X86_CONFIG(.event=0xc0)

?

That is, are there really bits we want to mask in there?

> +
> +	return hsw_get_event_constraints(cpuc, idx, event);
> +}