linux-kernel - [PATCH v2 3/3] ARM: mvebu: prefix coprocessor operand with p

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Message-Id: <09e394aa9368227a45144f169a680747a454c95b.1554757135.git.stefan@agner.ch>
Date:   Mon,  8 Apr 2019 22:59:55 +0200
From:   Stefan Agner <stefan@...er.ch>
To:     arm@...nel.org
Cc:     linux@...linux.org.uk, arnd@...db.de, ard.biesheuvel@...aro.org,
        robin.murphy@....com, nicolas.pitre@...aro.org,
        f.fainelli@...il.com, rjui@...adcom.com, sbranden@...adcom.com,
        bcm-kernel-feedback-list@...adcom.com, kgene@...nel.org,
        krzk@...nel.org, robh@...nel.org, ssantosh@...nel.org,
        jason@...edaemon.net, andrew@...n.ch, gregory.clement@...tlin.com,
        sebastian.hesselbarth@...il.com, tony@...mide.com,
        marc.w.gonzalez@...e.fr, mans@...sr.com, ndesaulniers@...gle.com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Stefan Agner <stefan@...er.ch>,
        Nicolas Pitre <nico@...xnic.net>
Subject: [PATCH v2 3/3] ARM: mvebu: prefix coprocessor operand with p

In every other instance where mrc is used the coprocessor operand
is prefix with p (e.g. p15). Use the p prefix in this case too.
This fixes a build issue when using LLVM's integrated assembler:
  arch/arm/mach-mvebu/coherency_ll.S:69:6: error: invalid operand for instruction
   mrc 15, 0, r3, cr0, cr0, 5
       ^
  arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction
   mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
       ^

Signed-off-by: Stefan Agner <stefan@...er.ch>
Acked-by: Nicolas Pitre <nico@...xnic.net>
---
 arch/arm/mach-mvebu/coherency_ll.S | 2 +-
 arch/arm/mach-mvebu/pmsu_ll.S      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 8b2fbc8b6bc6..2d962fe48821 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -66,7 +66,7 @@ ENDPROC(ll_get_coherency_base)
  * fabric registers
  */
 ENTRY(ll_get_coherency_cpumask)
-	mrc	15, 0, r3, cr0, cr0, 5
+	mrc	p15, 0, r3, cr0, cr0, 5
 	and	r3, r3, #15
 	mov	r2, #(1 << 24)
 	lsl	r3, r2, r3
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index c1fb713e9306..7aae9a25cfeb 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -16,7 +16,7 @@
 ENTRY(armada_38x_scu_power_up)
 	mrc     p15, 4, r1, c15, c0	@ get SCU base address
 	orr	r1, r1, #0x8		@ SCU CPU Power Status Register
-	mrc	15, 0, r0, cr0, cr0, 5	@ get the CPU ID
+	mrc	p15, 0, r0, cr0, cr0, 5	@ get the CPU ID
 	and	r0, r0, #15
 	add	r1, r1, r0
 	mov	r0, #0x0
-- 
2.21.0