lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 9 Apr 2019 02:43:23 +0000 From: Anson Huang <anson.huang@....com> To: "robh+dt@...nel.org" <robh+dt@...nel.org>, "mark.rutland@....com" <mark.rutland@....com>, "shawnguo@...nel.org" <shawnguo@...nel.org>, "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>, "kernel@...gutronix.de" <kernel@...gutronix.de>, "festevam@...il.com" <festevam@...il.com>, "a.zummo@...ertech.it" <a.zummo@...ertech.it>, "alexandre.belloni@...tlin.com" <alexandre.belloni@...tlin.com>, Aisheng Dong <aisheng.dong@....com>, "ulf.hansson@...aro.org" <ulf.hansson@...aro.org>, "sboyd@...nel.org" <sboyd@...nel.org>, Peng Fan <peng.fan@....com>, Daniel Baluta <daniel.baluta@....com>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "linux-rtc@...r.kernel.org" <linux-rtc@...r.kernel.org> CC: dl-linux-imx <linux-imx@....com> Subject: [PATCH V6 3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox RX doorbell mode is used for this function, this patch adds support for it. Signed-off-by: Anson Huang <Anson.Huang@....com> Reviewed-by: Dong Aisheng <aisheng.dong@....com> --- No changes. --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 0cb9398..70ef3db 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -21,6 +21,7 @@ mmc1 = &usdhc2; mmc2 = &usdhc3; serial0 = &adma_lpuart0; + mu1 = &lsio_mu1; }; cpus { @@ -117,7 +118,8 @@ scu { compatible = "fsl,imx-scu"; mbox-names = "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3"; + "rx0", "rx1", "rx2", "rx3", + "gip3"; mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 @@ -125,7 +127,8 @@ &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 - &lsio_mu1 1 3>; + &lsio_mu1 1 3 + &lsio_mu1 3 3>; clk: clock-controller { compatible = "fsl,imx8qxp-clk"; -- 2.7.4
Powered by blists - more mailing lists