linux-kernel - [PATCH V2 0/2] perf: Add Tremont support

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Message-Id: <1554922629-126287-1-git-send-email-kan.liang@linux.intel.com>
Date:   Wed, 10 Apr 2019 11:57:07 -0700
From:   kan.liang@...ux.intel.com
To:     peterz@...radead.org, mingo@...hat.com,
        linux-kernel@...r.kernel.org
Cc:     tglx@...utronix.de, acme@...nel.org, jolsa@...nel.org,
        eranian@...gle.com, alexander.shishkin@...ux.intel.com,
        ak@...ux.intel.com, Kan Liang <kan.liang@...ux.intel.com>
Subject: [PATCH V2 0/2] perf: Add Tremont support

From: Kan Liang <kan.liang@...ux.intel.com>

The patch series intends to add Tremont support for Linux perf.

The patch series is on top of Icelake V5 patch series (with Peter's cleanup patch).
https://lkml.org/lkml/2019/4/8/630

PATCH 1: A fix for Icelake V5 patch series (with Peter's cleanup patch).
         It can be merged back into "Subject: perf/x86/intel: Add Icelake support"
PATCH 2: Tremont core PMU support.

Changes since V1:
- The previous patch "perf/x86/intel: Support adaptive PEBS for fixed counters"
  will be merged back.
- New patch to fix the checking for instruction event.
- Allow instruction:ppp on generic purpose counter 0

Kan Liang (2):
  perf/x86/intel: Fix the checking for instruction event
  perf/x86/intel: Add Tremont core PMU support

 arch/x86/events/intel/core.c | 96 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 1 deletion(-)

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2.7.4