lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Fri, 12 Apr 2019 01:02:30 +0300 From: Dmitry Osipenko <digetx@...il.com> To: Peter De Schrijver <pdeschrijver@...dia.com>, Prashant Gaikwad <pgaikwad@...dia.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Thierry Reding <thierry.reding@...il.com>, Jonathan Hunter <jonathanh@...dia.com>, Joseph Lo <josephl@...dia.com> Cc: linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH v1 5/5] clk: tegra: divider: Mark Memory Controller clock as read-only The Memory Controller clock rate can't be simply changed and nothing in kernel need to change the rate, hence let's make the clock read-only. Signed-off-by: Dmitry Osipenko <digetx@...il.com> --- drivers/clk/tegra/clk-divider.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 205fe8ff63f0..f891bbb0d06d 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -175,6 +175,7 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, void __iomem *reg, spinlock_t *lock) { return clk_register_divider_table(NULL, name, parent_name, - CLK_IS_CRITICAL, reg, 16, 1, 0, - mc_div_table, lock); + CLK_IS_CRITICAL | + CLK_DIVIDER_READ_ONLY, + reg, 16, 1, 0, mc_div_table, lock); } -- 2.21.0
Powered by blists - more mailing lists