linux-kernel - [PATCH v2 0/6] arch: riscv: add board and SoC DT file support

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Date:   Thu, 11 Apr 2019 01:42:37 -0700
From:   Paul Walmsley <paul.walmsley@...ive.com>
To:     linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        devicetree@...r.kernel.org, robh+dt@...nel.org
Cc:     Paul Walmsley <paul.walmsley@...ive.com>
Subject: [PATCH v2 0/6] arch: riscv: add board and SoC DT file support

Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
architectures.  Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unleashed A00.

This second version of the patch set fixes several errors in the
original patch set, switches to an initial YAML-based description for CPU,
board SoC selection, and incorporates feedback from Rob Herring
<robh@...nel.org>.

Rob: it would be helpful if you could take a look at the YAML files to
make sure I'm not doing anything explicitly broken; I'm pretty naive
about the new YAML json-schema format.  The patches here are meant to
be starting points which will undoubtedly be refined later.  Similarly
we'll plan to convert our IP block binding documentation to the YAML
format over time as we develop more experience with it.

Boot-tested on v5.1-rc4 on a HiFive Unleashed A00 board, using the
BBL and open-source FSBL, with modifications to pass in the DTB
file generated by these patches.

This patch series can be found, along with the PRCI patch set
and the DT macro prerequisite patch, at:

https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.1-rc4

- Paul

Paul Walmsley (6):
  arch: riscv: add support for building DTB files from DT source data
  dt-bindings: riscv: sifive: add YAML documentation for the SiFive
    FU540
  dt-bindings: riscv: convert cpu binding to json-schema
  riscv: dts: add initial support for the SiFive FU540-C000 SoC
  riscv: dts: add initial board data for the SiFive HiFive Unleashed
  riscv: defconfig: enable ARCH_SIFIVE

 .../devicetree/bindings/riscv/cpus.yaml       | 274 ++++++++++++++++++
 .../devicetree/bindings/riscv/sifive.yaml     |  26 ++
 MAINTAINERS                                   |   9 +
 arch/riscv/Kconfig                            |   2 +
 arch/riscv/Kconfig.platforms                  |   8 +
 arch/riscv/boot/dts/Makefile                  |   2 +
 arch/riscv/boot/dts/sifive/Makefile           |   2 +
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 207 +++++++++++++
 .../dts/sifive/hifive-unleashed-a00-fu540.dts |  69 +++++
 arch/riscv/configs/defconfig                  |   1 +
 10 files changed, 600 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
 create mode 100644 arch/riscv/Kconfig.platforms
 create mode 100644 arch/riscv/boot/dts/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
 create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts

-- 
2.20.1