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Date: Thu, 11 Apr 2019 01:43:03 -0700 From: Paul Walmsley <paul.walmsley@...ive.com> To: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org Cc: Paul Walmsley <paul.walmsley@...ive.com>, Paul Walmsley <paul@...an.com>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Palmer Dabbelt <palmer@...ive.com>, Albert Ou <aou@...s.berkeley.edu> Subject: [PATCH 5/6] riscv: dts: add initial board data for the SiFive HiFive Unleashed Add initial board data for the SiFive HiFive Unleashed A00. Currently the data populated in this DT file describes the board DRAM configuration and the external clock sources that supply the PRCI. This second version adds onboard SPI device data, fixes the board's memory size, and adds changes based on comments from Rob Herring <robh+dt@...nel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@...ive.com> Signed-off-by: Paul Walmsley <paul@...an.com> Cc: Rob Herring <robh+dt@...nel.org> Cc: Mark Rutland <mark.rutland@....com> Cc: Palmer Dabbelt <palmer@...ive.com> Cc: Albert Ou <aou@...s.berkeley.edu> Cc: devicetree@...r.kernel.org Cc: linux-riscv@...ts.infradead.org Cc: linux-kernel@...r.kernel.org --- arch/riscv/boot/dts/sifive/Makefile | 2 + .../dts/sifive/hifive-unleashed-a00-fu540.dts | 69 +++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 arch/riscv/boot/dts/sifive/Makefile create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile new file mode 100644 index 000000000000..fb825db888df --- /dev/null +++ b/arch/riscv/boot/dts/sifive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00-fu540.dtb diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts new file mode 100644 index 000000000000..9d35e811a3aa --- /dev/null +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (Apache-2.0 OR GPL-2.0+) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00 (FU540-C000)"; + compatible = "sifive,hifive-unleashed-a00-fu540", + "sifive,hifive-unleashed-fu540", + "sifive,fu540-c000", "sifive-fu540"; + + chosen { + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@...00000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <RTCCLK_FREQ>; + clock-output-names = "rtcclk"; + }; +}; + +&qspi0 { + flash@0 { + compatible = "issi,is25wp256d", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; -- 2.20.1
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