lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 11 Apr 2019 13:24:46 -0700
From:   Stephen Boyd <>
To:     Matthias Brugger <>,
        Nicolas Boichat <>,
        Rob Herring <>,
        Stephen Boyd <>,
        Weiyi Lu <>
Cc:     James Liao <>,
        Fan Chen <>,,,,,,,
        Weiyi Lu <>
Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off

Quoting Weiyi Lu (2019-03-04 21:05:46)
> From: James Liao <>
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
> Signed-off-by: James Liao <>
> Acked-by: Michael Turquette <>
> Signed-off-by: Weiyi Lu <>
> ---

Applied to clk-next

Powered by blists - more mailing lists