linux-kernel - Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off

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Message-ID: <155501428642.20095.13010940386938154148@swboyd.mtv.corp.google.com>
Date:   Thu, 11 Apr 2019 13:24:46 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Nicolas Boichat <drinkcat@...omium.org>,
        Rob Herring <robh@...nel.org>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Weiyi Lu <weiyi.lu@...iatek.com>
Cc:     James Liao <jamesjj.liao@...iatek.com>,
        Fan Chen <fan.chen@...iatek.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
        srv_heupstream@...iatek.com, stable@...r.kernel.org,
        Weiyi Lu <weiyi.lu@...iatek.com>
Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off

Quoting Weiyi Lu (2019-03-04 21:05:46)
> From: James Liao <jamesjj.liao@...iatek.com>
> 
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
> 
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
> 
> Signed-off-by: James Liao <jamesjj.liao@...iatek.com>
> Acked-by: Michael Turquette <mturuqette@...libre.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> ---

Applied to clk-next