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Date:   Mon, 15 Apr 2019 17:29:47 -0400
From:   Gaël PORTAY <gael.portay@...labora.com>
To:     MyungJoo Ham <myungjoo.ham@...sung.com>,
        Kyungmin Park <kyungmin.park@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Rob Herring <robh+dt@...nel.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Enric Balletbo i Serra <enric.balletbo@...labora.com>,
        Lin Huang <hl@...k-chips.com>,
        Brian Norris <briannorris@...omium.org>,
        Douglas Anderson <dianders@...omium.org>,
        Klaus Goger <klaus.goger@...obroma-systems.com>,
        Derek Basehore <dbasehore@...omium.org>,
        Randy Li <ayaka@...lik.info>, linux-pm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org
Cc:     Mark Rutland <mark.rutland@....com>,
        Gaël PORTAY <gael.portay@...labora.com>
Subject: [PATCH v4 4/5] arm64: dts: rk3399: Add dfi and dmc nodes.

From: Lin Huang <hl@...k-chips.com>

These are required to support DDR DVFS on rk3399 platform.

Signed-off-by: Lin Huang <hl@...k-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
Signed-off-by: Gaël PORTAY <gael.portay@...labora.com>
---

Changes in v4:
- [PATCH v3 4/5] Remove board related DDR settings.

Changes in v3: None

Changes in v2:
- [PATCH 7/8] Reword the commit message to reflect the removal of
              rk3390-dram-default-timing.dts in v1.

Changes in v1:
- [RFC 8/10] Move rk3399-dram.h to dt-includes.
- [RFC 8/10] Put sdram default values under the dmc node.
- [RFC 8/10] Removed rk3399-dram-default-timing.dts

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index db9d948c0b03..87ee084fac89 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1885,6 +1885,25 @@
 		status = "disabled";
 	};
 
+	dfi: dfi@...30000 {
+		reg = <0x00 0xff630000 0x00 0x4000>;
+		compatible = "rockchip,rk3399-dfi";
+		rockchip,pmu = <&pmugrf>;
+		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru PCLK_DDR_MON>;
+		clock-names = "pclk_ddr_mon";
+		status = "disabled";
+	};
+
+	dmc: dmc {
+		compatible = "rockchip,rk3399-dmc";
+		rockchip,pmu = <&pmugrf>;
+		devfreq-events = <&dfi>;
+		clocks = <&cru SCLK_DDRC>;
+		clock-names = "dmc_clk";
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3399-pinctrl";
 		rockchip,grf = <&grf>;
-- 
2.21.0

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