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Message-ID: <CAGb2v66dY40zkQcVcyORZ-7RAkC1ATB9fTyRzabf-NyDKAustw@mail.gmail.com>
Date: Mon, 15 Apr 2019 22:39:08 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Maxime Ripard <maxime.ripard@...tlin.com>
Cc: Alessandro Zummo <a.zummo@...ertech.it>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>, linux-rtc@...r.kernel.org,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-sunxi <linux-sunxi@...glegroups.com>
Subject: Re: [linux-sunxi] [PATCH 0/3] Add basic support for RTC on Allwinner
H6 SoC
On Mon, Apr 15, 2019 at 10:33 PM Maxime Ripard
<maxime.ripard@...tlin.com> wrote:
>
> On Mon, Apr 15, 2019 at 04:22:22PM +0200, Ondřej Jirman wrote:
> > DT would still probably need a re-work in the future, if the PRCM clock
> > modeling the gate would be needed.
>
> Just reacting to that bit.
>
> I know we're pretty bad at this, and the documentation doesn't make it
> any easier, but if you have any idea of how it should be modelled
> next, then do that.
It seems to be just a clock gate, judging by previous (A80/A83T) SoCs.
However since we lack documents for the PRCM, we might need to poke
around to verify that it's actually there.
Or maybe we could ask Allwinner very specific questions, like:
- Does the PRCM have a gate controlling XO?
- Is it bit 2 in register 0x44 in the PRCM?
ChenYu
> There's no reason to push it to a later time, it makes everyone's life
> harder.
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>
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