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Message-Id: <1555536851-17462-15-git-send-email-fenghua.yu@intel.com>
Date: Wed, 17 Apr 2019 14:34:04 -0700
From: Fenghua Yu <fenghua.yu@...el.com>
To: "Thomas Gleixner" <tglx@...utronix.de>,
"Ingo Molnar" <mingo@...hat.com>, "Borislav Petkov" <bp@...en8.de>,
"H Peter Anvin" <hpa@...or.com>,
"Paolo Bonzini" <pbonzini@...hat.com>,
"Dave Hansen" <dave.hansen@...el.com>,
"Ashok Raj" <ashok.raj@...el.com>,
"Peter Zijlstra" <peterz@...radead.org>,
"Ravi V Shankar" <ravi.v.shankar@...el.com>,
"Xiaoyao Li " <xiaoyao.li@...el.com>,
"Christopherson Sean J" <sean.j.christopherson@...el.com>,
"Kalle Valo" <kvalo@...eaurora.org>,
"Michael Chan" <michael.chan@...adcom.com>
Cc: "linux-kernel" <linux-kernel@...r.kernel.org>,
"x86" <x86@...nel.org>, kvm@...r.kernel.org,
netdev@...r.kernel.org, linux-wireless@...r.kernel.org,
Fenghua Yu <fenghua.yu@...el.com>
Subject: [PATCH v7 14/21] x86/split_lock: Enable split lock detection by default
A split locked access locks bus and degrades overall memory access
performance. When split lock detection feature is enumerated, enable
the feature by default to find any split lock issue.
Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
---
arch/x86/kernel/cpu/intel.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 997d683d3c27..6a692d215bef 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -34,6 +34,8 @@
DEFINE_PER_CPU(u64, msr_test_ctl_cache);
EXPORT_PER_CPU_SYMBOL_GPL(msr_test_ctl_cache);
+static bool split_lock_detect_enable;
+
/*
* Just in case our CPU detection goes bad, or you have a weird system,
* allow a way to override the automatic disabling of MPX.
@@ -164,6 +166,23 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
return false;
}
+static void split_lock_update_msr(void *__unused)
+{
+ if (split_lock_detect_enable) {
+ msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT);
+ this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT);
+ } else {
+ msr_clear_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT);
+ this_cpu_and(msr_test_ctl_cache, ~TEST_CTL_SPLIT_LOCK_DETECT);
+ }
+}
+
+static void init_split_lock_detect(struct cpuinfo_x86 *c)
+{
+ if (cpu_has(c, X86_FEATURE_SPLIT_LOCK_DETECT))
+ split_lock_update_msr(NULL);
+}
+
static void early_init_intel(struct cpuinfo_x86 *c)
{
u64 misc_enable;
@@ -661,6 +680,8 @@ static void init_intel(struct cpuinfo_x86 *c)
{
early_init_intel(c);
+ init_split_lock_detect(c);
+
intel_workarounds(c);
/*
@@ -1032,9 +1053,22 @@ static const struct cpu_dev intel_cpu_dev = {
cpu_dev_register(intel_cpu_dev);
+#undef pr_fmt
+#define pr_fmt(fmt) "x86/split lock detection: " fmt
+
+static void show_split_lock_detection_info(void)
+{
+ if (split_lock_detect_enable)
+ pr_info("enabled\n");
+ else
+ pr_info("disabled\n");
+}
+
static void __init set_split_lock_detect(void)
{
setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
+ split_lock_detect_enable = true;
+ show_split_lock_detection_info();
}
void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c)
--
2.19.1
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