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Message-Id: <fd223d1dcf5be1f83863e881fa3db931b5c84601.1555917711.git.baolin.wang@linaro.org>
Date:   Tue, 23 Apr 2019 10:26:21 +0800
From:   Baolin Wang <baolin.wang@...aro.org>
To:     lgirdwood@...il.com, broonie@...nel.org, perex@...ex.cz,
        robh+dt@...nel.org, mark.rutland@....com, tiwai@...e.com
Cc:     linux-kernel@...r.kernel.org, alsa-devel@...a-project.org,
        baolin.wang@...aro.org, orsonzhai@...il.com, zhang.lyra@...il.com,
        devicetree@...r.kernel.org
Subject: [PATCH v2 1/2] dt-bindings: ASoC: Add Spreadtrum multi-channel data transfer support

On Spreadtrum platform, the audio subsystem will use the multi-channel
data transfer controller to transfer sound stream between audio subsystem
and other AP/CP subsystem.

It can support 10 DAC channel and 10 ADC channel, and each channel has
512 bytes depth data fifo. Moreover each channel can be used DMA mode
or interrupt mode to transfer data.

Signed-off-by: Baolin Wang <baolin.wang@...aro.org>
---
Changes from v1:
 - Move the documentation into sound/.
---
 .../devicetree/bindings/sound/sprd-mcdt.txt        |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/sprd-mcdt.txt

diff --git a/Documentation/devicetree/bindings/sound/sprd-mcdt.txt b/Documentation/devicetree/bindings/sound/sprd-mcdt.txt
new file mode 100644
index 0000000..274ba0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/sprd-mcdt.txt
@@ -0,0 +1,19 @@
+Spreadtrum Multi-Channel Data Transfer Binding
+
+The Multi-channel data transfer controller is used for sound stream
+transmission between audio subsystem and other AP/CP subsystem. It
+supports 10 DAC channel and 10 ADC channel, and each channel can be
+configured with DMA mode or interrupt mode.
+
+Required properties:
+- compatible: Should be "sprd,sc9860-mcdt".
+- reg: Should contain registers address and length.
+- interrupts: Should contain one interrupt shared by all channel.
+
+Example:
+
+mcdt@...90000 {
+	compatible = "sprd,sc9860-mcdt";
+	reg = <0 0x41490000 0 0x170>;
+	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+};
-- 
1.7.9.5

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