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Message-ID: <20190424135852.08810789@coco.lan>
Date: Wed, 24 Apr 2019 13:58:52 -0300
From: Mauro Carvalho Chehab <mchehab+samsung@...nel.org>
To: Changbin Du <changbin.du@...il.com>
Cc: Jonathan Corbet <corbet@....net>,
Bjorn Helgaas <bhelgaas@...gle.com>, rjw@...ysocki.net,
linux-pci@...r.kernel.org, linux-doc@...r.kernel.org,
linux-kernel@...r.kernel.org, tglx@...utronix.de, mingo@...hat.com,
x86@...nel.org, fenghua.yu@...el.com,
linuxppc-dev@...ts.ozlabs.org, linux-acpi@...r.kernel.org,
linux-gpio@...r.kernel.org
Subject: Re: [PATCH v4 35/63] Documentation: PCI: convert
endpoint/pci-test-function.txt to reST
Em Wed, 24 Apr 2019 00:29:04 +0800
Changbin Du <changbin.du@...il.com> escreveu:
> This converts the plain text documentation to reStructuredText format and
> add it to Sphinx TOC tree. No essential content change.
>
> Signed-off-by: Changbin Du <changbin.du@...il.com>
> Acked-by: Bjorn Helgaas <bhelgaas@...gle.com>
> ---
> Documentation/PCI/endpoint/index.rst | 1 +
> ...est-function.txt => pci-test-function.rst} | 32 +++++++++++--------
> 2 files changed, 20 insertions(+), 13 deletions(-)
> rename Documentation/PCI/endpoint/{pci-test-function.txt => pci-test-function.rst} (84%)
>
> diff --git a/Documentation/PCI/endpoint/index.rst b/Documentation/PCI/endpoint/index.rst
> index 3951de9f923c..b680a3fc4fec 100644
> --- a/Documentation/PCI/endpoint/index.rst
> +++ b/Documentation/PCI/endpoint/index.rst
> @@ -9,3 +9,4 @@ PCI Endpoint Framework
>
> pci-endpoint
> pci-endpoint-cfs
> + pci-test-function
> diff --git a/Documentation/PCI/endpoint/pci-test-function.txt b/Documentation/PCI/endpoint/pci-test-function.rst
> similarity index 84%
> rename from Documentation/PCI/endpoint/pci-test-function.txt
> rename to Documentation/PCI/endpoint/pci-test-function.rst
> index 5916f1f592bb..ba02cddcec37 100644
> --- a/Documentation/PCI/endpoint/pci-test-function.txt
> +++ b/Documentation/PCI/endpoint/pci-test-function.rst
> @@ -1,5 +1,10 @@
> - PCI TEST
> - Kishon Vijay Abraham I <kishon@...com>
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +=================
> +PCI Test Function
> +=================
> +
> +:Author: Kishon Vijay Abraham I <kishon@...com>
>
> Traditionally PCI RC has always been validated by using standard
> PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
> @@ -23,30 +28,31 @@ The PCI endpoint test device has the following registers:
> 8) PCI_ENDPOINT_TEST_IRQ_TYPE
> 9) PCI_ENDPOINT_TEST_IRQ_NUMBER
>
> -*) PCI_ENDPOINT_TEST_MAGIC
> +* PCI_ENDPOINT_TEST_MAGIC
Same comment as on a previous patch. I suspect that the author's intention
for all stuff under Documentation/PCI/endpoint/ (or perhaps this is due
tothe markup language he uses) is to have:
*) foo
as a chapter, e. g. the right conversion would be, instead:
PCI_ENDPOINT_TEST_MAGIC
=======================
(same applies to the other similar markups here and on other files under
the endpoint/ directory)
>
> This register will be used to test BAR0. A known pattern will be written
> and read back from MAGIC register to verify BAR0.
>
> -*) PCI_ENDPOINT_TEST_COMMAND:
> +* PCI_ENDPOINT_TEST_COMMAND:
>
> This register will be used by the host driver to indicate the function
> that the endpoint device must perform.
>
> -Bitfield Description:
> +Bitfield Description::
> +
> Bit 0 : raise legacy IRQ
> Bit 1 : raise MSI IRQ
> Bit 2 : raise MSI-X IRQ
> Bit 3 : read command (read data from RC buffer)
> Bit 4 : write command (write data to RC buffer)
> - Bit 5 : copy command (copy data from one RC buffer to another
> - RC buffer)
> + Bit 5 : copy command (copy data from one RC buffer to another RC buffer)
Please use a table instead:
Bitfield Description:
===== =======================================================
Bit 0 raise legacy IRQ
Bit 1 raise MSI IRQ
Bit 2 raise MSI-X IRQ
Bit 3 read command (read data from RC buffer)
Bit 4 write command (write data to RC buffer)
Bit 5 copy command (copy data from one RC buffer to another
RC buffer)
===== =======================================================
>
> -*) PCI_ENDPOINT_TEST_STATUS
> +* PCI_ENDPOINT_TEST_STATUS
>
> This register reflects the status of the PCI endpoint device.
>
> -Bitfield Description:
> +Bitfield Description::
> +
> Bit 0 : read success
> Bit 1 : read fail
> Bit 2 : write success
> @@ -57,17 +63,17 @@ Bitfield Description:
> Bit 7 : source address is invalid
> Bit 8 : destination address is invalid
Same here:
Bitfield Description:
===== ==============================
Bit 0 read success
Bit 1 read fail
Bit 2 write success
Bit 3 write fail
Bit 4 copy success
Bit 5 copy fail
Bit 6 IRQ raised
Bit 7 source address is invalid
Bit 8 destination address is invalid
===== ==============================
>
> -*) PCI_ENDPOINT_TEST_SRC_ADDR
> +* PCI_ENDPOINT_TEST_SRC_ADDR
>
> This register contains the source address (RC buffer address) for the
> COPY/READ command.
>
> -*) PCI_ENDPOINT_TEST_DST_ADDR
> +* PCI_ENDPOINT_TEST_DST_ADDR
>
> This register contains the destination address (RC buffer address) for
> the COPY/WRITE command.
>
> -*) PCI_ENDPOINT_TEST_IRQ_TYPE
> +* PCI_ENDPOINT_TEST_IRQ_TYPE
>
> This register contains the interrupt type (Legacy/MSI) triggered
> for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
> @@ -77,7 +83,7 @@ Possible types:
You need a blank line before - MSI, in order to not use a bold font for
"Possible types:".
> - MSI : 1
> - MSI-X : 2
>
> -*) PCI_ENDPOINT_TEST_IRQ_NUMBER
> +* PCI_ENDPOINT_TEST_IRQ_NUMBER
>
> This register contains the triggered ID interrupt.
>
Same here: ou need a blank line on this text:
Admissible values:
+
- Legacy : 0
- MSI : [1 .. 32]
- MSI-X : [1 .. 2048]
In order to avoid using bold font for "Admissible values".
Thanks,
Mauro
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