linux-kernel - Re: [RFC PATCH for 5.2 10/10] rseq/selftests: mips: use break instruction for RSEQ

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Message-ID: <20190424220609.4kryfcgsv46iu3ds@pburton-laptop>
Date:   Wed, 24 Apr 2019 22:06:18 +0000
From:   Paul Burton <paul.burton@...s.com>
To:     Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
CC:     Peter Zijlstra <peterz@...radead.org>,
        "Paul E . McKenney" <paulmck@...ux.vnet.ibm.com>,
        Boqun Feng <boqun.feng@...il.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-api@...r.kernel.org" <linux-api@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Andy Lutomirski <luto@...capital.net>,
        Dave Watson <davejwatson@...com>, Paul Turner <pjt@...gle.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Russell King <linux@....linux.org.uk>,
        Ingo Molnar <mingo@...hat.com>,
        "H . Peter Anvin" <hpa@...or.com>,
        Andi Kleen <andi@...stfloor.org>, Chris Lameter <cl@...ux.com>,
        Ben Maurer <bmaurer@...com>,
        Steven Rostedt <rostedt@...dmis.org>,
        Josh Triplett <josh@...htriplett.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Michael Kerrisk <mtk.manpages@...il.com>,
        Joel Fernandes <joelaf@...gle.com>,
        Shuah Khan <shuah@...nel.org>, James Hogan <jhogan@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        "linux-mips@...ux-mips.org" <linux-mips@...ux-mips.org>
Subject: Re: [RFC PATCH for 5.2 10/10] rseq/selftests: mips: use break
 instruction for RSEQ_SIG

Hi Mathieu,

On Wed, Apr 24, 2019 at 11:25:02AM -0400, Mathieu Desnoyers wrote:
> diff --git a/tools/testing/selftests/rseq/rseq-mips.h b/tools/testing/selftests/rseq/rseq-mips.h
> index fe3eabcdcbe5..eb53a6adfbbb 100644
> --- a/tools/testing/selftests/rseq/rseq-mips.h
> +++ b/tools/testing/selftests/rseq/rseq-mips.h
> @@ -7,7 +7,11 @@
>   * (C) Copyright 2016-2018 - Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
>   */
>  
> -#define RSEQ_SIG	0x53053053
> +/*
> + * RSEQ_SIG uses the break instruction. The instruction pattern is
> + *	0350000d        break    0x350
> + */
> +#define RSEQ_SIG	0x0350000d

My apologies for taking a while to get back to you on the various ISAs &
endian issues here, but I think we'll want this to be something like:

#if defined(__nanomips__)
# ifdef __MIPSEL__
#  define RSEQ_SIG	0x03500010
# else
#  define RSEQ_SIG	0x00100350
# endif
#elif defined(__mips_micromips)
# ifdef __MIPSEL__
#  define RSEQ_SIG	0xd4070000
# else
#  define RSEQ_SIG	0x0000d407
# endif
#else
# define RSEQ_SIG	0x0350000d
#endif

For plain old MIPS the .word directive will be fine endian-wise, but for
microMIPS & nanoMIPS we need to take into account that the instruction
stream is encoded as 16b halfwords & swap those accordingly for little
endian.

Thanks,
    Paul