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Message-Id: <20190424231444.20876-5-digetx@gmail.com>
Date: Thu, 25 Apr 2019 02:14:41 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Joseph Lo <josephl@...dia.com>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>
Cc: linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v1 4/7] clocksource/drivers/tegra: Replace readl/writel with relaxed versions
The readl/writel functions are inserting memory barrier to ensure that
outstanding memory writes are completed, this results in L2 cache syncing
being done on Tegra20 and Tegra30 which isn't a very cheap operation.
Replace all readl/writel occurrences in the code with the relaxed versions
since there is no need for the memory-access syncing.
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
drivers/clocksource/timer-tegra20.c | 38 ++++++++++++++---------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 01d713f20a85..d171a214f066 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -64,9 +64,9 @@ static int tegra_timer_set_next_event(unsigned long cycles,
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PTV_EN |
- ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
- reg_base + TIMER_PTV);
+ writel_relaxed(TIMER_PTV_EN |
+ ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
+ reg_base + TIMER_PTV);
return 0;
}
@@ -75,7 +75,7 @@ static int tegra_timer_shutdown(struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(0, reg_base + TIMER_PTV);
+ writel_relaxed(0, reg_base + TIMER_PTV);
return 0;
}
@@ -84,8 +84,8 @@ static int tegra_timer_set_periodic_fixed_rate(struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PTV_EN | TIMER_PTV_PER | (1000000 / HZ - 1),
- reg_base + TIMER_PTV);
+ writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (1000000 / HZ - 1),
+ reg_base + TIMER_PTV);
return 0;
}
@@ -94,9 +94,9 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PTV_EN | TIMER_PTV_PER |
- ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
- reg_base + TIMER_PTV);
+ writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER |
+ ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+ reg_base + TIMER_PTV);
return 0;
}
@@ -106,7 +106,7 @@ static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
struct clock_event_device *evt = (struct clock_event_device *)dev_id;
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+ writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
evt->event_handler(evt);
return IRQ_HANDLED;
@@ -116,12 +116,12 @@ static void tegra_timer_suspend(struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+ writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
}
static void tegra_timer_resume(struct clock_event_device *evt)
{
- writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
+ writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
}
static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
@@ -145,8 +145,8 @@ static int tegra_timer_setup(unsigned int cpu)
{
struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
- writel(0, timer_of_base(to) + TIMER_PTV);
- writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
+ writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
+ writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
enable_irq(to->clkevt.irq);
@@ -170,12 +170,12 @@ static int tegra_timer_stop(unsigned int cpu)
static u64 notrace tegra_read_sched_clock(void)
{
- return readl(timer_reg_base + TIMERUS_CNTR_1US);
+ return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
}
static unsigned long tegra_delay_timer_read_counter_long(void)
{
- return readl(timer_reg_base + TIMERUS_CNTR_1US);
+ return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
}
static struct delay_timer tegra_delay_timer = {
@@ -191,8 +191,8 @@ static struct delay_timer tegra_delay_timer = {
*/
static u64 tegra_rtc_read_ms(void)
{
- u32 ms = readl(rtc_base + RTC_MILLISECONDS);
- u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
+ u32 ms = readl_relaxed(rtc_base + RTC_MILLISECONDS);
+ u32 s = readl_relaxed(rtc_base + RTC_SHADOW_SECONDS);
return (u64)s * MSEC_PER_SEC + ms;
}
@@ -291,7 +291,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
goto out;
}
- writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
+ writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
for_each_possible_cpu(cpu) {
struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
--
2.21.0
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