linux-kernel - Re: [RFC PATCH for 5.2 10/10] rseq/selftests: mips: use break instruction for RSEQ

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Message-ID: <2047127593.1305.1556148177478.JavaMail.zimbra@efficios.com>
Date:   Wed, 24 Apr 2019 19:22:57 -0400 (EDT)
From:   Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
To:     Paul Burton <paul.burton@...s.com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        "Paul E . McKenney" <paulmck@...ux.vnet.ibm.com>,
        Boqun Feng <boqun.feng@...il.com>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-api <linux-api@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Andy Lutomirski <luto@...capital.net>,
        Dave Watson <davejwatson@...com>, Paul Turner <pjt@...gle.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Russell King <linux@....linux.org.uk>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>, Andi Kleen <andi@...stfloor.org>,
        Chris Lameter <cl@...ux.com>, Ben Maurer <bmaurer@...com>,
        rostedt <rostedt@...dmis.org>,
        Josh Triplett <josh@...htriplett.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Michael Kerrisk <mtk.manpages@...il.com>,
        Joel Fernandes <joelaf@...gle.com>, shuah <shuah@...nel.org>,
        James Hogan <jhogan@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        linux-mips <linux-mips@...ux-mips.org>
Subject: Re: [RFC PATCH for 5.2 10/10] rseq/selftests: mips: use break
 instruction for RSEQ_SIG

----- On Apr 24, 2019, at 7:17 PM, Paul Burton paul.burton@...s.com wrote:

> Hi Mathieu,
> 
> On Wed, Apr 24, 2019 at 07:12:03PM -0400, Mathieu Desnoyers wrote:
>> Does the following comment above the forest of #ifdef work for you ?
>> 
>> /*
>>  * RSEQ_SIG uses the break instruction. The instruction pattern is:
>>  *
>>  * On MIPS:
>>  *      0350000d        break     0x350
>>  *
>>  * On nanoMIPS32:
>>  *      00100350        break     0x350
>>  *
>>  * On microMIPS:
>>  *      0000d407        break     0x350
>>  *
>>  * For nanoMIPS32 and microMIPS, the instruction stream is encoded as 16-bit
>>  * halfwords, so the signature halfwords need to be swapped accordingly for
>>  * little-endian.
>>  */
> 
> I'd probably just say nanoMIPS rather than nanoMIPS32, because when we
> get nanoMIPS64 in the future it'll be a superset of nanoMIPS32 & the
> break encoding will be the same.

Done.

> 
> But otherwise it looks good to me :)

Great! I've added your "Suggested-by" tag to the patch.

Thanks,

Mathieu

> 
> Thanks,
>     Paul

-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com