linux-kernel - [RFC][PATCH 0/5] atomic: Fixes to smp_mb__{before,after}

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Message-Id: <20190424123656.484227701@infradead.org>
Date:   Wed, 24 Apr 2019 14:36:56 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     stern@...land.harvard.edu, akiyks@...il.com,
        andrea.parri@...rulasolutions.com, boqun.feng@...il.com,
        dlustig@...dia.com, dhowells@...hat.com, j.alglave@....ac.uk,
        luc.maranget@...ia.fr, npiggin@...il.com, paulmck@...ux.ibm.com,
        peterz@...radead.org, will.deacon@....com
Cc:     linux-kernel@...r.kernel.org, torvalds@...ux-foundation.org
Subject: [RFC][PATCH 0/5] atomic: Fixes to smp_mb__{before,after}_atomic() and mips...

Hi,

This all started when Andrea Parri found a 'surprising' behaviour for x86:

  http://lkml.kernel.org/r/20190418125412.GA10817@andrea

Basically we fail for:

	*x = 1;
	atomic_inc(u);
	smp_mb__after_atomic();
	r0 = *y;

Because, while the atomic_inc() implies memory order, it
(surprisingly) does not provide a compiler barrier. This then allows
the compiler to re-order like so:

	atomic_inc(u);
	*x = 1;
	smp_mb__after_atomic();
	r0 = *y;

Which the CPU is then allowed to re-order (under TSO rules) like:

	atomic_inc(u);
	r0 = *y;
	*x = 1;

And this very much was not intended.

This had me audit all the (strong) architectures that had weak
smp_mb__{before,after}_atomic: ia64, mips, sparc, s390, x86, xtensa.

Of those, only x86 and mips were affected. Looking at MIPS to solve this, led
to the other MIPS patches.

Only the x86 patch is actually compile tested, the MIPS things are fresh from
the keyboard.