linux-kernel - Re: [PATCH 1/4] glibc: Perform rseq(2) registration at C startup and thread creation (v7)

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Date:   Thu, 25 Apr 2019 01:41:30 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@...ux-mips.org>
To:     Paul Burton <paul.burton@...s.com>
cc:     Mathieu Desnoyers <mathieu.desnoyers@...icios.com>,
        Carlos O'Donell <codonell@...hat.com>,
        Will Deacon <will.deacon@....com>,
        Boqun Feng <boqun.feng@...il.com>,
        heiko carstens <heiko.carstens@...ibm.com>,
        gor <gor@...ux.ibm.com>, schwidefsky <schwidefsky@...ibm.com>,
        "Russell King, ARM Linux" <linux@...linux.org.uk>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Paul Mackerras <paulus@...ba.org>,
        Michael Ellerman <mpe@...erman.id.au>,
        carlos <carlos@...hat.com>, Florian Weimer <fweimer@...hat.com>,
        Joseph Myers <joseph@...esourcery.com>,
        Szabolcs Nagy <szabolcs.nagy@....com>,
        libc-alpha <libc-alpha@...rceware.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ben Maurer <bmaurer@...com>,
        Peter Zijlstra <peterz@...radead.org>,
        "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
        Dave Watson <davejwatson@...com>, Paul Turner <pjt@...gle.com>,
        Rich Felker <dalias@...c.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-api <linux-api@...r.kernel.org>
Subject: Re: [PATCH 1/4] glibc: Perform rseq(2) registration at C startup
 and thread creation (v7)

On Wed, 24 Apr 2019, Paul Burton wrote:

> > > Any idea why 0x7273 is not accepted by my assembler ?
> 
> I don't know why the assembler wants a smaller immediate than the
> instruction encoding allows... There's a comment in the binutils file
> include/opcode/mips.h that reads:
> 
> > A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
> > breakpoint instruction are not defined; Kane says the breakpoint code
> > field in BREAK is 20 bits; yet MIPS assemblers and debuggers only use
> > ten bits).  An optional two-operand form of break/sdbbp allows the
> > lower ten bits to be set too, and MIPS32 and later architectures allow
> > 20 bits to be set with a signal operand (using CODE20).
> 
> I suspect there's some history here that predates my involvement (or
> possibly just predates me).

 A useful explanation is in the Linux kernel (always good to look there), 
in arch/mips/kernel/traps.c:

	/*
	 * There is the ancient bug in the MIPS assemblers that the break
	 * code starts left to bit 16 instead to bit 6 in the opcode.
	 * Gas is bug-compatible, but not always, grrr...
	 * We handle both cases with a simple heuristics.  --macro
	 */

Unfortunately the bug has been carried over to the microMIPS instruction 
encoding in libopcodes for no reason (i.e. likely by copying the table 
mechanically without analysing it) and I didn't catch it when upstreaming.  
We should have permitted setting all bits in the 20-bit code field in the 
microMIPS encoding with a single operand, but you need two, like with the 
regular MIPS instruction set.

 The note on the MIPS32 assembly ISA permitting to set all the 20 bits 
with a single operand is a stale comment referring to the situation before 
binutils commit 1586d91e32ea ("/ 0 should send SIGFPE not SIGTRAP..."), 
<https://sourceware.org/ml/binutils/2004-07/msg00260.html>, which 
addressed a user ABI compatibility issue as discussed upthread here: 
<https://sourceware.org/ml/binutils/2004-06/msg00188.html> and previously: 
<https://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=40C9F5A4.2050606%40avtrex.com>.

 As this is my mistake with the stale note, I have applied a fix to 
binutils now, commit cd0923370be1 ("MIPS/include: opcode/mips.h: Update 
stale comment for CODE20 operand"), so that it is clear that it is only 
SDBBP that accepts a single 20-bit operand for the code field (for the 
MIPS32 and later ISAs).

 FWIW,

  Maciej