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Message-ID: <155621658525.15276.10875911078203745396@swboyd.mtv.corp.google.com>
Date: Thu, 25 Apr 2019 11:23:05 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: andy.tang@....com, mturquette@...libre.com
Cc: robh+dt@...nel.org, mark.rutland@....com,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Yuantian Tang <andy.tang@....com>
Subject: Re: [PATCH 2/2] clk: qoriq: add more PLL divider clocks support
Quoting andy.tang@....com (2019-04-22 02:15:09)
> From: Yuantian Tang <andy.tang@....com>
>
> More PLL divider clocks are needed by clock consumer IP. So enlarge
> the PLL divider array to accommodate more divider clocks.
>
> Signed-off-by: Yuantian Tang <andy.tang@....com>
> ---
Applied to clk-next
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