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Message-ID: <BYAPR07MB47095561D7C58860CD8C7400DD3E0@BYAPR07MB4709.namprd07.prod.outlook.com>
Date: Fri, 26 Apr 2019 10:39:49 +0000
From: Pawel Laszczak <pawell@...ence.com>
To: Roger Quadros <rogerq@...com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
CC: "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
"felipe.balbi@...ux.intel.com" <felipe.balbi@...ux.intel.com>,
"mark.rutland@....com" <mark.rutland@....com>,
"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
"hdegoede@...hat.com" <hdegoede@...hat.com>,
"heikki.krogerus@...ux.intel.com" <heikki.krogerus@...ux.intel.com>,
"andy.shevchenko@...il.com" <andy.shevchenko@...il.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"jbergsagel@...com" <jbergsagel@...com>,
"nsekhar@...com" <nsekhar@...com>, "nm@...com" <nm@...com>,
Suresh Punnoose <sureshp@...ence.com>,
"peter.chen@....com" <peter.chen@....com>,
Rahul Kumar <kurahul@...ence.com>
Subject: RE: [PATCH v6 1/6] dt-bindings: add binding for USBSS-DRD controller.
Hi Roger,
>On 10/04/2019 10:48, Pawel Laszczak wrote:
>> This patch aim at documenting USB related dt-bindings for the
>> Cadence USBSS-DRD controller.
>>
>> Signed-off-by: Pawel Laszczak <pawell@...ence.com>
>> Reviewed-by: Rob Herring <robh@...nel.org>
>>
>> ---
>> .../devicetree/bindings/usb/cdns-usb3.txt | 30 +++++++++++++++++++
>> 1 file changed, 30 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/usb/cdns-usb3.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/cdns-usb3.txt b/Documentation/devicetree/bindings/usb/cdns-usb3.txt
>> new file mode 100644
>> index 000000000000..1d2b449e3cb4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/cdns-usb3.txt
>> @@ -0,0 +1,30 @@
>> +Binding for the Cadence USBSS-DRD controller
>> +
>> +Required properties:
>> + - reg: Physical base address and size of the controller's register areas.
>> + Controller has 3 different regions:
>> + region 1 - HOST registers area
>> + region 2 - DEVICE registers area
>> + region 3 - OTG/DRD registers area
>> + - reg-names - register memory area names:
>> + "xhci" - for HOST registers space
>> + "dev" - for DEVICE registers space
>> + "otg" - for OTG/DRD registers space
>> + - compatible: Should contain: "cdns,usb3-1.0.0" or "cdns,usb3-1.0.1"
>> + - interrupts: Interrupts used by cdns3 controller.
>> +
>> +Optional properties:
>> + - maximum-speed : valid arguments are "super-speed", "high-speed" and
>> + "full-speed"; refer to usb/generic.txt
>> + - dr_mode: Should be one of "host", "peripheral" or "otg".
>> + - phys: reference to the USB PHY
>
>In your test platform is this a 2.0PHY or 3.0PHY? Typical platforms will have both.
>Is there any power-on sequencing requirements for powering up these PHYs vs powering up the controller?
>
Generally, my testing platform is based on PCIe, so I don’t use dts. PHY initialization on my testing platform
has been hidden in FPGA implementation. We are using DTS in simulation but there we don't have a PHYs.
I think that you have right, and we should have here two USB2.0 and USB3.0 phy.
I have to look at how it looks in other drivers and improve this this file and maybe CDNS3 driver too.
>> +
>> +Example:
>> + usb@...00000 {
>> + compatible = "cdns,usb3-1.0.1";
>> + interrupts = <USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0xf3000000 0x10000 /* memory area for HOST registers */
>> + 0xf3010000 0x10000 /* memory area for DEVICE registers */
>> + 0xf3020000 0x10000>; /* memory area for OTG/DRD registers */
>> + reg-names = "xhci", "dev", "otg";
>> + };
>>
>
cheers,
Pawel
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