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Message-ID: <20190426132821.GB14432@lunn.ch>
Date:   Fri, 26 Apr 2019 15:28:21 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Serge Semin <fancer.lancer@...il.com>
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Serge Semin <Sergey.Semin@...latforms.ru>,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] net: phy: realtek: Add rtl8211e rx/tx delays config

On Fri, Apr 26, 2019 at 12:30:10PM +0300, Serge Semin wrote:
> The hidden RGMII configs register utilization was found in the
> rtl8211e U-boot driver:
> https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99
> 
> It confirms that the register bits field must control the so called
> configuration pins described in the table 12-13 of the official PHY
> datasheet:
> 8:6 = PHY Address
> 5:4 = Auto-Negotiation
> 3 = Interface Mode Select
> 2 = RX Delay
> 1 = TX Delay
> 0 = SELRGV

> +static int rtl8211e_config_init(struct phy_device *phydev)
> +{
> +	int ret, oldpage;
> +	u16 val = 0;
> +
> +	ret = genphy_config_init(phydev);
> +	if (ret < 0)
> +		return ret;
> +
> +	/* enable TX/RX delay for rgmii-* modes, otherwise disable it */
> +	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
> +		val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
> +	else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
> +		val = RTL8211E_TX_DELAY;
> +	else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
> +		val = RTL8211E_RX_DELAY;

Hi Serge

You need to look for PHY_INTERFACE_MODE_RGMII and disable the bits.
For any other value, and in particular PHY_INTERFACE_MODE_NA, you
should leave the bits alone.

As you found out, u-boot knows how to program these bits. There are
probably boards out there which rely on u-boot doing this, and the PHY
driver then not messing with the bits. The way to indicate it should
not mess with the bits is to not have a phy-mode property in DT, which
results in PHY_INTERFACE_MODE_NA.

	Andrew

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