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Date:   Fri, 26 Apr 2019 20:32:20 -0700 (PDT)
From:   Paul Walmsley <>
To:     Stephen Boyd <>
cc:     Paul Walmsley <>,,,,,
        Paul Walmsley <>,
        Wesley Terpstra <>,
        Palmer Dabbelt <>,
        Michael Turquette <>,
        Megan Wachs <>
Subject: Re: [PATCH v3 1/3] clk: analogbits: add Wide-Range PLL library

On Fri, 26 Apr 2019, Stephen Boyd wrote:

> Quoting Paul Walmsley (2019-04-11 01:27:32)
> > Add common library code for the Analog Bits Wide-Range PLL (WRPLL) IP
> > block, as implemented in TSMC CLN28HPC.
> I haven't deeply reviewed at all, but I already get two problems when
> compile testing these patches. I can fix them up if nothing else needs
> fixing.
> drivers/clk/analogbits/wrpll-cln28hpc.c:165 __wrpll_calc_divq() warn: should 'target_rate << divq' be a 64 bit type?
> drivers/clk/sifive/fu540-prci.c:214:16: error: return expression in void function

Hmm, that's odd.  I will definitely take a look and repost.

- Paul

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