linux-kernel - [PATCH 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20190429093631.10799-1-geert+renesas@glider.be>
Date:   Mon, 29 Apr 2019 11:36:26 +0200
From:   Geert Uytterhoeven <geert+renesas@...der.be>
To:     Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <marc.zyngier@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Simon Horman <horms@...ge.net.au>,
        Magnus Damm <magnus.damm@...il.com>,
        Chris Brandt <chris.brandt@...esas.com>
Cc:     devicetree@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Geert Uytterhoeven <geert+renesas@...der.be>
Subject: [PATCH 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches

	Hi all,

Unlike on most other Renesas SoCs, the GPIO controller block on RZ/A1
SoCs lack interrupt functionality.  While the GPIOs can be routed to the
GIC as pin interrupts, this is of limited use, as the PL390 GIC supports
rising edge and high-level interrupts only.

Fortunately RZ/A1 SoCs contain a small front-end for the GIC, allowing
to use up to 8 external interrupts, with configurable sense select.

Hence this patch series adds DT bindings and a driver for this
front-end, adds a device node for it in the RZ/A1H DTS, and uses it to
enable support for the 3 input switches on the Renesas RSK+RZA1
development board.

I expect this driver to be reusable for RZ/A2, after adding a match
entry with .gic_spi_base = 4.
  - Should this information come from DT instead?
  - Originally I had interrupts properties in DT to define the mapping
    from external interrupts to GIC interrupts (cfr. "renesas,irqc",
    which also calls request_irq()), but other similar drivers seem to
    hardcode this information in the driver, so I went that route.

Dependencies:
  - Patch 3 depends on patch 2,
  - Patch 4 can be applied as soon as the DT bindings in patch 1 have
    been accepted,
  - Patch 5 depends on patch 4.

This has been tested on RSK+RZA1 with evtest and s2ram wake-up.
I have verified proper operation of low-level and rising/falling sense
select, too.

Thanks for your comments!

Geert Uytterhoeven (5):
  dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt
    Controller
  irqchip: Add Renesas RZ/A1 Interrupt Controller driver
  soc: renesas: Enable RZ/A1 IRQC on RZ/A1H
  ARM: dts: r7s72100: Add IRQC device node
  ARM: dts: rskrza1: Add input switches

 .../renesas,rza1-irqc.txt                     |  27 ++
 arch/arm/boot/dts/r7s72100-rskrza1.dts        |  38 +++
 arch/arm/boot/dts/r7s72100.dtsi               |   8 +
 drivers/irqchip/Kconfig                       |   4 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-renesas-rza1.c            | 238 ++++++++++++++++++
 drivers/soc/renesas/Kconfig                   |   1 +
 7 files changed, 317 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
 create mode 100644 drivers/irqchip/irq-renesas-rza1.c

-- 
2.17.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds