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Message-ID: <CAK8P3a0gex0ffvX9zQDV=N7g6q7UAxxYRn2PeAbbAgrd1wTvQg@mail.gmail.com>
Date: Mon, 29 Apr 2019 13:13:32 +0200
From: Arnd Bergmann <arnd@...db.de>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Greg Ungerer <gerg@...ux-m68k.org>,
Angelo Dureghello <angelo@...am.it>,
Logan Gunthorpe <logang@...tatee.com>,
Thomas Gleixner <tglx@...utronix.de>,
Kate Stewart <kstewart@...uxfoundation.org>,
Philippe Ombredanne <pombredanne@...b.com>,
Greg KH <gregkh@...uxfoundation.org>,
"Linux/m68k" <linux-m68k@...r.kernel.org>,
Linux-Arch <linux-arch@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: endianness swapped
On Mon, Apr 29, 2019 at 10:44 AM Geert Uytterhoeven
<geert@...ux-m68k.org> wrote:
> On Sun, Apr 28, 2019 at 3:59 PM Greg Ungerer <gerg@...ux-m68k.org> wrote:
> > On 28/4/19 7:21 pm, Arnd Bergmann wrote:
> > > On Sun, Apr 28, 2019 at 10:46 AM Geert Uytterhoeven
> > > <geert@...ux-m68k.org> wrote:
> > >>
> > >> Orthogonal to how Coldfire's read[wl]() should be fixed, I find it a bit
> > >> questionable to swap data twice on big endian architectures.
> > >
> > > I would expect that the compiler is capable of detecting a double
> > > swap and optimize it out. Even if it can't, there are not that many
> > > instances of io{read,write}{16,32}be in the kernel, so the increase
> > > in kernel image size from a double swap should be limited to a
> > > few extra instructions, and the runtime overhead should be
> > > negligible compared to the bus access.
>
> Probably the overhead is not negligible on old m68k...
Maybe the I/O devices are faster than I expected then. I was guessing
that there is still a factor of 100x or more between going to an on-chip
bus and single byterev register-to-register instruction.
I did notice that __arch_swab32() is an inline assembly, so the
compiler has no way of eliminating the double swap, but
setting CONFIG_ARCH_USE_BUILTIN_BSWAP makes it
do the right thing.
Arnd
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