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Date:   Mon, 29 Apr 2019 22:42:40 -0700
From:   Atish Patra <atish.patra@....com>
To:     Palmer Dabbelt <palmer@...ive.com>
Cc:     "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
        "anup@...infault.org" <anup@...infault.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "zong@...estech.com" <zong@...estech.com>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH] RISC-V: Add an Image header that boot loader can parse.

On 4/29/19 4:40 PM, Palmer Dabbelt wrote:
> On Tue, 23 Apr 2019 16:25:06 PDT (-0700), atish.patra@....com wrote:
>> Currently, last stage boot loaders such as U-Boot can accept only
>> uImage which is an unnecessary additional step in automating boot flows.
>>
>> Add a simple image header that boot loaders can parse and directly
>> load kernel flat Image. The existing booting methods will continue to
>> work as it is.
>>
>> Tested on both QEMU and HiFive Unleashed using OpenSBI + U-Boot + Linux.
>>
>> Signed-off-by: Atish Patra <atish.patra@....com>
>> ---
>>   arch/riscv/include/asm/image.h | 32 ++++++++++++++++++++++++++++++++
>>   arch/riscv/kernel/head.S       | 28 ++++++++++++++++++++++++++++
>>   2 files changed, 60 insertions(+)
>>   create mode 100644 arch/riscv/include/asm/image.h
>>
>> diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h
>> new file mode 100644
>> index 000000000000..76a7e0d4068a
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/image.h
>> @@ -0,0 +1,32 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +
>> +#ifndef __ASM_IMAGE_H
>> +#define __ASM_IMAGE_H
>> +
>> +#define RISCV_IMAGE_MAGIC	"RISCV"
>> +
>> +#ifndef __ASSEMBLY__
>> +/*
>> + * struct riscv_image_header - riscv kernel image header
>> + *
>> + * @code0:		Executable code
>> + * @code1:		Executable code
>> + * @text_offset:	Image load offset
>> + * @image_size:		Effective Image size
>> + * @reserved:		reserved
>> + * @magic:		Magic number
>> + * @reserved:		reserved
>> + */
>> +
>> +struct riscv_image_header {
>> +	u32 code0;
>> +	u32 code1;
>> +	u64 text_offset;
>> +	u64 image_size;
>> +	u64 res1;
>> +	u64 magic;
>> +	u32 res2;
>> +	u32 res3;
>> +};
> 
> I don't want to invent our own file format.  Is there a reason we can't just
> use something standard?  Off the top of my head I can think of ELF files and
> multiboot.
> 

Additional header is required to accommodate PE header format. 
Currently, this is only used for booti command but it will be reused for 
EFI headers as well. Linux kernel Image can pretend as an EFI 
application if PE/COFF header is present. This removes the need of an 
explicit EFI boot loader and EFI firmware can directly load Linux 
(obviously after EFI stub implementation for RISC-V).

ARM64 follows the similar header format as well.
https://www.kernel.org/doc/Documentation/arm64/booting.txt

Regards,
Atish

>> +#endif /* __ASSEMBLY__ */
>> +#endif /* __ASM_IMAGE_H */
>> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
>> index fe884cd69abd..154647395601 100644
>> --- a/arch/riscv/kernel/head.S
>> +++ b/arch/riscv/kernel/head.S
>> @@ -19,9 +19,37 @@
>>   #include <asm/thread_info.h>
>>   #include <asm/page.h>
>>   #include <asm/csr.h>
>> +#include <asm/image.h>
>>
>>   __INIT
>>   ENTRY(_start)
>> +	/*
>> +	 * Image header expected by Linux boot-loaders. The image header data
>> +	 * structure is described in asm/image.h.
>> +	 * Do not modify it without modifying the structure and all bootloaders
>> +	 * that expects this header format!!
>> +	 */
>> +	/* jump to start kernel */
>> +	j _start_kernel
>> +	/* reserved */
>> +	.word 0
>> +	.balign 8
>> +#if __riscv_xlen == 64
>> +	/* Image load offset(2MB) from start of RAM */
>> +	.dword 0x200000
>> +#else
>> +	/* Image load offset(4MB) from start of RAM */
>> +	.dword 0x400000
>> +#endif
>> +	/* Effective size of kernel image */
>> +	.dword _end - _start
>> +	.dword 0
>> +	.asciz RISCV_IMAGE_MAGIC
>> +	.word 0
>> +	.word 0
>> +
>> +.global _start_kernel
>> +_start_kernel:
>>   	/* Mask all interrupts */
>>   	csrw sie, zero
> 
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