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Date:   Thu, 2 May 2019 14:41:39 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     John Garry <john.garry@...wei.com>, linux-kernel@...r.kernel.org
Cc:     Mark Rutland <mark.rutland@....com>,
        Peter Zijlstra <peterz@...radead.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Ingo Molnar <mingo@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Jiri Olsa <jolsa@...hat.com>,
        "moderated list:ARM PMU PROFILING AND DEBUGGING" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] perf vendor events arm64: Add Cortex-A72 events

On 4/11/19 6:01 AM, John Garry wrote:
> On 07/04/2019 22:34, Florian Fainelli wrote:
>> The Cortex-A72 supports all ARMv8 recommended events up to the
>> RC_ST_SPEC (0x91) event, create an appropriate JSON file for mapping
>> those events and update the mapfile.csv for matching the Cortex-A72 MIDR
>> to that file.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
>> ---
>>  .../arm64/arm/cortex-a72/core-imp-def.json    | 206 ++++++++++++++++++
>>  tools/perf/pmu-events/arch/arm64/mapfile.csv  |   1 +
>>  2 files changed, 207 insertions(+)
>>  create mode 100644
>> tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>>
>> diff --git
>> a/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>> b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>> new file mode 100644
>> index 000000000000..eb82fc8529c6
>> --- /dev/null
>> +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>> @@ -0,0 +1,206 @@
>> +[
>> +    {
>> +        "ArchStdEvent": "L1D_CACHE_RD",
>> +    },
>> +    {
>> +        "ArchStdEvent": "L1D_CACHE_WR",
>> +    },
>> +    {
>> +        "ArchStdEvent": "L1D_CACHE_REFILL_RD",
>> +    },
>> +    {
>> +        "ArchStdEvent": "L1D_CACHE_REFILL_WR",
>> +    },
>> +    {
>> +        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
> 
> I'm just checking the A72 TRM, and this does not seem to be included,
> that being event number 0x44.
> 
>> +    },
>> +    {
>> +        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
>> +    },
> 
> Or this.
> 
>> +    {
>> +        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
>> +    },
>> +    {
> 
> Please check this.

Indeed, thanks!
-- 
Florian

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