linux-kernel - Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller

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Date:   Thu, 2 May 2019 15:05:08 +0530
From:   Yash Shah <yash.shah@...ive.com>
To:     Sudeep Holla <sudeep.holla@....com>
Cc:     Rob Herring <robh@...nel.org>, linux-riscv@...ts.infradead.org,
        devicetree@...r.kernel.org, Palmer Dabbelt <palmer@...ive.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-kernel@...r.kernel.org, aou@...s.berkeley.edu,
        mark.rutland@....com, Sachin Ghadi <sachin.ghadi@...ive.com>
Subject: Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller

On Thu, May 2, 2019 at 2:40 PM Sudeep Holla <sudeep.holla@....com> wrote:
>
>
> Sorry if I created confusion. I just wanted a note saying all the properties
> in ePAPR/DeviceTree specification applies for this platform. That would
> help me check if the standard cacheinfo infrastruction works as is or not.

Sure, will add this note.

- Yash
>
> --
> Regards,
> Sudeep