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Message-ID: <8161008c-fafd-a89f-d2d8-413224844cd2@gmail.com>
Date: Fri, 3 May 2019 12:00:21 +0200
From: Marek Vasut <marek.vasut@...il.com>
To: Simon Goldschmidt <simon.k.r.goldschmidt@...il.com>,
linux-mtd@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org,
Brian Norris <computersforpeace@...il.com>,
Richard Weinberger <richard@....at>,
David Woodhouse <dwmw2@...radead.org>,
Boris Brezillon <bbrezillon@...nel.org>,
Tudor Ambarus <tudor.ambarus@...rochip.com>
Subject: Re: [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a
On 5/3/19 10:53 AM, Simon Goldschmidt wrote:
> Tested on socfpga cyclone5 where this is required to ensure that the
> boot rom can access this flash after warm reboot.
Are you sure _all_ variants of the N25Q256 support 4NB opcodes ?
I think there were some which didn't, but I might be wrong.
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@...il.com>
> ---
>
> drivers/mtd/spi-nor/spi-nor.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index fae147452..4cdec2cc2 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1874,7 +1874,7 @@ static const struct flash_info spi_nor_ids[] = {
> { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>
--
Best regards,
Marek Vasut
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