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Date:   Fri, 3 May 2019 13:27:39 +0200
From:   Marek Vasut <marek.vasut@...il.com>
To:     Simon Goldschmidt <simon.k.r.goldschmidt@...il.com>
Cc:     linux-mtd@...ts.infradead.org,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Brian Norris <computersforpeace@...il.com>,
        Richard Weinberger <richard@....at>,
        David Woodhouse <dwmw2@...radead.org>,
        Boris Brezillon <bbrezillon@...nel.org>,
        Tudor Ambarus <tudor.ambarus@...rochip.com>
Subject: Re: [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a

On 5/3/19 12:37 PM, Simon Goldschmidt wrote:
> On Fri, May 3, 2019 at 12:00 PM Marek Vasut <marek.vasut@...il.com> wrote:
>>
>> On 5/3/19 10:53 AM, Simon Goldschmidt wrote:
>>> Tested on socfpga cyclone5 where this is required to ensure that the
>>> boot rom can access this flash after warm reboot.
>>
>> Are you sure _all_ variants of the N25Q256 support 4NB opcodes ?
>> I think there were some which didn't, but I might be wrong.
> 
> Oh, damn, you're right. The documentation [1] statest that 4-byte erase and
> program opcodes are only supported for part numbers N25Q256A83ESF40x,
> N25Q256A83E1240x and N25QA83ESFA0F.

;-)

> Any idea of how I can still enable 4-byte opcodes for my chip?
Maybe SFDP tables contains some information whether the chip supports
the 4B opcodes ?

-- 
Best regards,
Marek Vasut

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