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Date:   Sun, 5 May 2019 07:41:19 +0200
From:   Oleksij Rempel <o.rempel@...gutronix.de>
To:     Chuanhong Guo <gch981213@...il.com>
Cc:     Andrew Lunn <andrew@...n.ch>, Paul Burton <paul.burton@...s.com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        James Hogan <jhogan@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Jay Cliburn <jcliburn@...il.com>,
        Chris Snook <chris.snook@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Mark Rutland <mark.rutland@....com>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        linux-mips@...r.kernel.org,
        open list <linux-kernel@...r.kernel.org>,
        devicetree@...r.kernel.org, John Crispin <john@...ozen.org>,
        Felix Fietkau <nbd@....name>, netdev@...r.kernel.org
Subject: Re: [PATCH v3 3/3] net: ethernet: add ag71xx driver

On Sat, May 04, 2019 at 11:40:53PM +0800, Chuanhong Guo wrote:
> Hi!
> 
> On Mon, Apr 22, 2019 at 9:28 PM Andrew Lunn <andrew@...n.ch> wrote:
> > [...]
> > > +     /*
> > > +      * On most (all?) Atheros/QCA SoCs dual eth interfaces are not equal.
> > > +      *
> > > +      * That is to say eth0 can not work independently. It only works
> > > +      * when eth1 is working.
> > > +      */
> >
> > Please could you explain that some more? Is there just one MDIO bus
> > shared by two ethernet controllers? If so, it would be better to have
> > the MDIO bus controller as a separate driver.
> 
> mdio registers exists on both ethernet blocks. And due to how reset
> works on this ethernet IP, it's hard to split it into a separated
> driver. (Only asserting both eth and mdio resets together will reset
> everything including register values.)
> The reason why gmac1 should be brought up first is that on some chips,
> mdio on gmac0 connects to nothing and phy used by gmac0 is on mdio bus
> of gmac1.

It could be implemented as mfd device. Not sure if it is worth it.
Pro/contra argumentation is welcome.

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