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Message-Id: <1557142026-15949-1-git-send-email-yash.shah@sifive.com>
Date: Mon, 6 May 2019 16:57:05 +0530
From: Yash Shah <yash.shah@...ive.com>
To: linux-edac@...r.kernel.org, linux-riscv@...ts.infradead.org,
palmer@...ive.com, bp@...en8.de, james.morse@....com
Cc: paul.walmsley@...ive.com, linux-kernel@...r.kernel.org,
aou@...s.berkeley.edu, mchehab@...nel.org, sachin.ghadi@...ive.com,
davem@...emloft.net, gregkh@...uxfoundation.org,
nicolas.ferre@...rochip.com, paulmck@...ux.ibm.com,
Yash Shah <yash.shah@...ive.com>
Subject: [PATCH v2] EDAC support for SiFive SoCs
Adds an EDAC platform driver for SiFive SoCs.
This patch was earlier part of the patch series:
'L2 cache controller and EDAC support for SiFive SoCs'
https://lkml.org/lkml/2019/4/15/320
In order to merge L2 cache controller driver without any dependency on EDAC,
this EDAC patch is re-posted separately with updated MAINTAINERS entry.
This patch depends on patch
'RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs'
https://lkml.org/lkml/2019/5/6/255
The EDAC driver registers for notifier events from the L2 cache controller
driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events
The patch is based on Linux 5.1-rc2 and tested on HiFive Unleashed board
with additional board related patches needed for testing can be found at
dev/yashs/L2_cache_controller branch of:
https://github.com/yashshah7/riscv-linux.git
Changes since v1
- Move extern definition into sifive_l2_cache header file
- Replace NOTIFY_STOP with NOTIFY_OK in ecc_err_event()
- Other minor fixes based upon comments against v1
Yash Shah (1):
edac: sifive: Add EDAC platform driver for SiFive SoCs
MAINTAINERS | 6 +++
arch/riscv/Kconfig | 1 +
drivers/edac/Kconfig | 6 +++
drivers/edac/Makefile | 1 +
drivers/edac/sifive_edac.c | 119 +++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 133 insertions(+)
create mode 100644 drivers/edac/sifive_edac.c
--
1.9.1
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