lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20190507063902.GA2085@tuxbook-pro>
Date:   Mon, 6 May 2019 23:39:02 -0700
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Brian Masney <masneyb@...tation.org>
Cc:     robdclark@...il.com, sean@...rly.run,
        dri-devel@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org,
        freedreno@...ts.freedesktop.org, airlied@...ux.ie, daniel@...ll.ch,
        linux-kernel@...r.kernel.org, linus.walleij@...aro.org
Subject: Re: [PATCH RFC 4/6] ARM: dts: msm8974: add display support

On Sun 05 May 06:04 PDT 2019, Brian Masney wrote:
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
[..]
> +			dsi0: dsi@...22800 {
> +				status = "disabled";
> +
> +				compatible = "qcom,mdss-dsi-ctrl";
> +				reg = <0xfd922800 0x1f8>;
> +				reg-names = "dsi_ctrl";
> +
> +				interrupt-parent = <&mdss>;
> +				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +
> +				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
> +				                  <&mmcc PCLK0_CLK_SRC>;
> +				assigned-clock-parents = <&dsi_phy0 0>,
> +				                         <&dsi_phy0 1>;
> +
> +				clocks = <&mmcc MDSS_MDP_CLK>,
> +				         <&mmcc MDSS_AHB_CLK>,
> +				         <&mmcc MDSS_AXI_CLK>,
> +				         <&mmcc MDSS_BYTE0_CLK>,
> +				         <&mmcc MDSS_PCLK0_CLK>,
> +				         <&mmcc MDSS_ESC0_CLK>,
> +				         <&mmcc MMSS_MISC_AHB_CLK>;
> +				clock-names = "mdp_core",
> +				              "iface",
> +				              "bus",
> +				              "byte",
> +				              "pixel",
> +				              "core",
> +				              "core_mmss";

Unless I enable MMSS_MMSSNOC_AXI_CLK and MMSS_S0_AXI_CLK I get some
underrun error from DSI. You don't see anything like this?

(These clocks are controlled by msm_bus downstream and should be driven
by interconnect upstream)


Apart from this, I think this looks nice. Happy to see the progress.

Regards,
Bjorn

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ