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Message-ID: <20190508104614.42481-1-wen.he_1@nxp.com>
Date: Wed, 8 May 2019 10:44:39 +0000
From: Wen He <wen.he_1@....com>
To: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>
CC: Leo Li <leoyang.li@....com>, Wen He <wen.he_1@....com>
Subject: [v5] arm64: dts: ls1028a: Add properties for Mali DP500 node
The LS1028A has a LCD controller and Displayport interface that
connects to eDP and Displayport connectors on the LS1028A board.
This patch enables the LCD controller driver on the LS1028A.
Signed-off-by: Alison Wang <alison.wang@....com>
Signed-off-by: Wen He <wen.he_1@....com>
Reviewed-by: Liviu Dudau <liviu.dudau@....com>
Reviewed-by: Rob Herring <robh@...nel.org>
---
change in v5:
- Reviewed by from Rob, thanks.
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index b04581249f0b..c0a13f9e5b95 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -70,6 +70,27 @@
clock-output-names = "sysclk";
};
+ dpclk: clock-dp {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names= "dpclk";
+ };
+
+ aclk: clock-axi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <650000000>;
+ clock-output-names= "aclk";
+ };
+
+ pclk: clock-apb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <650000000>;
+ clock-output-names= "pclk";
+ };
+
reboot {
compatible ="syscon-reboot";
regmap = <&dcfg>;
@@ -433,4 +454,21 @@
};
};
};
+
+ malidp0: display@...0000 {
+ compatible = "arm,mali-dp500";
+ reg = <0x0 0xf080000 0x0 0x10000>;
+ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+ <0 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "DE", "SE";
+ clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>;
+ clock-names = "pxlclk", "mclk", "aclk", "pclk";
+ arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+
+ port {
+ dp0_out: endpoint {
+
+ };
+ };
+ };
};
--
2.17.1
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