linux-kernel - Re: [v2 4/5] drm/mediatek: add frame size control

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Message-ID: <1557284354.31731.9.camel@mtksdaap41>
Date:   Wed, 8 May 2019 10:59:14 +0800
From:   CK Hu <ck.hu@...iatek.com>
To:     Jitao Shi <jitao.shi@...iatek.com>
CC:     Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>,
        "Mark Rutland" <mark.rutland@....com>,
        Ian Campbell <ijc+devicetree@...lion.org.uk>,
        Kumar Gala <galak@...eaurora.org>, <linux-pwm@...r.kernel.org>,
        David Airlie <airlied@...ux.ie>,
        "Matthias Brugger" <matthias.bgg@...il.com>,
        Thierry Reding <treding@...dia.com>,
        "Ajay Kumar" <ajaykumar.rs@...sung.com>,
        Inki Dae <inki.dae@...sung.com>,
        "Rahul Sharma" <rahul.sharma@...sung.com>,
        Sean Paul <seanpaul@...omium.org>,
        Vincent Palatin <vpalatin@...omium.org>,
        Andy Yan <andy.yan@...k-chips.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        "Russell King" <rmk+kernel@....linux.org.uk>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <dri-devel@...ts.freedesktop.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <srv_heupstream@...iatek.com>,
        Sascha Hauer <kernel@...gutronix.de>,
        <yingjoe.chen@...iatek.com>, <eddie.huang@...iatek.com>,
        <cawa.cheng@...iatek.com>, <bibby.hsieh@...iatek.com>,
        <stonea168@....com>
Subject: Re: [v2 4/5] drm/mediatek: add frame size control

Hi, Jitao:

On Tue, 2019-04-16 at 14:05 +0800, Jitao Shi wrote:
> Our new DSI chip has frame size control.
> So add the driver data to control for different chips.
> 

Reviewed-by: CK Hu <ck.hu@...iatek.com>

> Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dsi.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index be42405a0a78..458a700ce74c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -78,6 +78,7 @@
>  #define DSI_VBP_NL		0x24
>  #define DSI_VFP_NL		0x28
>  #define DSI_VACT_NL		0x2C
> +#define DSI_SIZE_CON		0x38
>  #define DSI_HSA_WC		0x50
>  #define DSI_HBP_WC		0x54
>  #define DSI_HFP_WC		0x58
> @@ -162,6 +163,7 @@ struct phy;
>  struct mtk_dsi_driver_data {
>  	const u32 reg_cmdq_off;
>  	bool has_shadow_ctl;
> +	bool has_size_ctl;
>  };
>  
>  struct mtk_dsi {
> @@ -430,6 +432,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
>  	writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
>  	writel(vm->vactive, dsi->regs + DSI_VACT_NL);
>  
> +	if (dsi->driver_data->has_size_ctl)
> +		writel(vm->vactive << 16 | vm->hactive, dsi->regs + DSI_SIZE_CON);
> +
>  	horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
>  
>  	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)