linux-kernel - Re: [PATCH v1 3/3] clk: qcom: rcg: update the DFS macro for RCG

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 10 May 2019 08:28:39 +0530
From:   Taniya Das <tdas@...eaurora.org>
To:     Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>
Cc:     Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 3/3] clk: qcom: rcg: update the DFS macro for RCG

Hello Stephen,

Thanks for the review.

On 5/9/2019 10:57 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-05-08 11:24:55)
>> Update the init data name for each of the dynamic frequency switch
>> controlled clock associated with the RCG clock name, so that it can be
>> generated as per the hardware plan. Thus update the macro accordingly.
>>
>> Signed-off-by: Taniya Das <tdas@...eaurora.org>
> 
> This patch doesn't make any sense to me.
> 
>> ---
>>   drivers/clk/qcom/clk-rcg.h    |  2 +-
>>   drivers/clk/qcom/gcc-sdm845.c | 96 +++++++++++++++++++++----------------------
>>   2 files changed, 49 insertions(+), 49 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
>> index 5562f38..e40e8f8 100644
>> --- a/drivers/clk/qcom/clk-rcg.h
>> +++ b/drivers/clk/qcom/clk-rcg.h
>> @@ -171,7 +171,7 @@ struct clk_rcg_dfs_data {
>>   };
>>
>>   #define DEFINE_RCG_DFS(r) \
>> -       { .rcg = &r##_src, .init = &r##_init }
>> +       { .rcg = &r, .init = &r##_init }
> 
> Why do we need to rename the init data?
> 

We want to manage the init data as the clock source name, so that we 
could manage to auto generate our code. So that we do not have to 
re-name the clock init data manually if the DFS source names gets 
updated at any point of time.

>>
>>   extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
>>                                      const struct clk_rcg_dfs_data *rcgs,
>> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
>> index 7131dcf..a76178b 100644
>> --- a/drivers/clk/qcom/gcc-sdm845.c
>> +++ b/drivers/clk/qcom/gcc-sdm845.c
>> @@ -408,7 +408,7 @@ enum {
>>          { }
>>   };
>>
>> -static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
>> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
>>          .name = "gcc_qupv3_wrap0_s0_clk_src",
>>          .parent_names = gcc_parent_names_0,
>>          .num_parents = 4,
>> @@ -3577,22 +3577,22 @@ enum {
>>   MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
>>
>>   static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
>> -       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
>> +       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
> 
> I've trimmed the above to try and see what's changed but it doesn't make
> sense still.
> 

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--