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Date: Sun, 12 May 2019 12:48:50 +0200 From: Guido Günther <agx@...xcpu.org> To: Kishon Vijay Abraham I <kishon@...com>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>, Pengutronix Kernel Team <kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>, NXP Linux Team <linux-imx@....com>, Thierry Reding <treding@...dia.com>, Andreas Färber <afaerber@...e.de>, Martin Blumenstingl <martin.blumenstingl@...glemail.com>, Heiko Stuebner <heiko@...ech.de>, Johan Hovold <johan@...nel.org>, Lucas Stach <l.stach@...gutronix.de>, Abel Vesa <abel.vesa@....com>, Li Jun <jun.li@....com>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, dri-devel@...ts.freedesktop.org, Robert Chiras <robert.chiras@....com>, Sam Ravnborg <sam@...nborg.org>, Maxime Ripard <maxime.ripard@...tlin.com> Subject: [PATCH v11 1/2] dt-bindings: phy: Add documentation for mixel dphy Add support for the MIXEL DPHY IP as found on NXP's i.MX8MQ SoCs. Signed-off-by: Guido Günther <agx@...xcpu.org> Reviewed-by: Sam Ravnborg <sam@...nborg.org> Reviewed-by: Rob Herring <robh@...nel.org> Reviewed-by: Fabio Estevam <festevam@...il.com> --- .../bindings/phy/mixel,mipi-dsi-phy.txt | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt new file mode 100644 index 000000000000..9b23407233c0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt @@ -0,0 +1,29 @@ +Mixel DSI PHY for i.MX8 + +The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the +MIPI-DSI IP from Northwest Logic). It represents the physical layer for the +electrical signals for DSI. + +Required properties: +- compatible: Must be: + - "fsl,imx8mq-mipi-dphy" +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: Must contain the following entries: + - "phy_ref": phandle and specifier referring to the DPHY ref clock +- reg: the register range of the PHY controller +- #phy-cells: number of cells in PHY, as defined in + Documentation/devicetree/bindings/phy/phy-bindings.txt + this must be <0> + +Optional properties: +- power-domains: phandle to power domain + +Example: + dphy: dphy@...0030 { + compatible = "fsl,imx8mq-mipi-dphy"; + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + clock-names = "phy_ref"; + reg = <0x30a00300 0x100>; + power-domains = <&pd_mipi0>; + #phy-cells = <0>; + }; -- 2.20.1
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