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Date: Mon, 13 May 2019 10:36:18 +0530 From: Vidya Sagar <vidyas@...dia.com> To: <lorenzo.pieralisi@....com>, <bhelgaas@...gle.com>, <robh+dt@...nel.org>, <mark.rutland@....com>, <thierry.reding@...il.com>, <jonathanh@...dia.com>, <kishon@...com>, <catalin.marinas@....com>, <will.deacon@....com>, <jingoohan1@...il.com>, <gustavo.pimentel@...opsys.com> CC: <mperttunen@...dia.com>, <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <kthota@...dia.com>, <mmaddireddy@...dia.com>, <vidyas@...dia.com>, <sagar.tv@...il.com> Subject: [PATCH V6 07/15] PCI: dwc: Add support to enable CDM register check Add support to enable CDM (Configuration Dependent Module) register check for any data corruption based on the device-tree flag 'enable-cdm-check'. Signed-off-by: Vidya Sagar <vidyas@...dia.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@...opsys.com> --- Changes since [v5]: * None Changes since [v4]: * None Changes since [v3]: * None Changes since [v2]: * Changed code and commit description to reflect change in flag from 'cdm-check' to 'enable-cdm-check' Changes since [v1]: * This is a new patch in v2 series drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++ drivers/pci/controller/dwc/pcie-designware.h | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index e46d19f61c9c..574245a63af5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -521,4 +521,11 @@ void dw_pcie_setup(struct dw_pcie *pci) break; } dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + + if (of_property_read_bool(np, "enable-cdm-check")) { + val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); + val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | + PCIE_PL_CHK_REG_CHK_REG_START; + dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); + } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index fff284098117..55e9c941e280 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -86,6 +86,15 @@ #define PCIE_MISC_CONTROL_1_OFF 0x8BC #define PCIE_DBI_RO_WR_EN BIT(0) +#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20 +#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) +#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) +#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16) +#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17) +#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18) + +#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28 + /* * iATU Unroll-specific register definitions * From 4.80 core version the address translation will be made by unroll -- 2.17.1
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