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Date: Tue, 14 May 2019 20:13:43 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Jerome Brunet <jbrunet@...libre.com>
Cc: Neil Armstrong <narmstrong@...libre.com>,
Kevin Hilman <khilman@...libre.com>,
linux-amlogic@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] clk: meson: g12a: fix gp0 and hifi ranges
On Mon, May 13, 2019 at 2:45 PM Jerome Brunet <jbrunet@...libre.com> wrote:
>
> While some SoC samples are able to lock with a PLL factor of 55, others
> samples can't. ATM, a minimum of 60 appears to work on all the samples
> I have tried.
>
> Even with 60, it sometimes takes a long time for the PLL to eventually
> lock. The documentation says that the minimum rate of these PLLs DCO
> should be 3GHz, a factor of 125. Let's use that to be on the safe side.
>
> With factor range changed, the PLL seems to lock quickly (enough) so far.
> It is still unclear if the range was the only reason for the delay.
>
> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> Signed-off-by: Jerome Brunet <jbrunet@...libre.com>
this matches with what Amlogic does in their 4.9 vendor kernel from
buildroot-openlinux-A113-201901:
$ grep -P "\tPLL_RATE" kernel/aml-4.9/drivers/amlogic/clk/g12a/g12a.h
| cut -d',' -f2 | tr -s " " | sort -u | head -n5
125
126
128
129
132
based on that:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
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