lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 15 May 2019 02:42:08 +0000
From:   Wen He <wen.he_1@....com>
To:     "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "liviu.dudau@....com" <liviu.dudau@....com>
CC:     Leo Li <leoyang.li@....com>, Wen He <wen.he_1@....com>
Subject: [v1] drm/arm/mali-dp: Disable checking for required pixel clock rate

Disable checking for required pixel clock rate if ARCH_LAYERSCPAE
is enable.

Signed-off-by: Alison Wang <alison.wang@....com>
Signed-off-by: Wen He <wen.he_1@....com>
---
change in description:
	- This check that only supported one pixel clock required clock rate
	compare with dts node value. but we have supports 4 pixel clock
	for ls1028a board.
 drivers/gpu/drm/arm/malidp_crtc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c
index 56aad288666e..bb79223d9981 100644
--- a/drivers/gpu/drm/arm/malidp_crtc.c
+++ b/drivers/gpu/drm/arm/malidp_crtc.c
@@ -36,11 +36,13 @@ static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc,
 
 	if (req_rate) {
 		rate = clk_round_rate(hwdev->pxlclk, req_rate);
+#ifndef CONFIG_ARCH_LAYERSCAPE
 		if (rate != req_rate) {
 			DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
 					 req_rate);
 			return MODE_NOCLOCK;
 		}
+#endif
 	}
 
 	return MODE_OK;
-- 
2.17.1

Powered by blists - more mailing lists