i40e: Debug hash inputs

From: Alexander Duyck <alexander.h.duyck@linux.intel.com>


---
 drivers/net/ethernet/intel/i40e/i40e_main.c |   52 +++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 65c2b9d2652b..c0a7f66babd9 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -10998,6 +10998,58 @@ static int i40e_pf_config_rss(struct i40e_pf *pf)
 		((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
 	hena |= i40e_pf_get_default_rss_hena(pf);
 
+	for (ret = 64; ret--;) {
+		u64 hash_inset_orig, hash_inset_update;
+
+		if (!(hena & (1ull << ret)))
+			continue;
+
+		/* Read initial input set value for flow type */
+		hash_inset_orig = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, ret));
+		hash_inset_orig <<= 32;
+		hash_inset_orig |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, ret));
+
+		/* Copy value so we can compare later */
+		hash_inset_update = hash_inset_orig;
+
+		/* We should be looking at either the entire IPv6 or IPv4
+		 * mask being set. If only part of the IPv6 mask is set, but
+		 * the IPv4 mask is not then we have a garbage mask value
+		 * and need to reset it.
+		 */
+		switch (hash_inset_orig & I40E_L3_V6_SRC_MASK) {
+		case I40E_L3_V6_SRC_MASK:
+		case I40E_L3_SRC_MASK:
+		case 0:
+			break;
+		default:
+			hash_inset_update &= ~I40E_L3_V6_SRC_MASK;
+			hash_inset_update |= I40E_L3_SRC_MASK;
+		}
+
+		switch (hash_inset_orig & I40E_L3_V6_DST_MASK) {
+		case I40E_L3_V6_DST_MASK:
+		case I40E_L3_DST_MASK:
+		case 0:
+			break;
+		default:
+			hash_inset_update &= ~I40E_L3_V6_DST_MASK;
+			hash_inset_update |= I40E_L3_DST_MASK;
+		}
+
+		if (hash_inset_update != hash_inset_orig) {
+			dev_warn(&pf->pdev->dev,
+				 "flow type: %d update input mask from:0x%016llx, to:0x%016llx\n",
+				 ret,
+				 hash_inset_orig, hash_inset_update);
+			i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, ret),
+					  (u32)hash_inset_update);
+			hash_inset_update >>= 32;
+			i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, ret),
+					  (u32)hash_inset_update);
+		}
+	}
+
 	i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
 	i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));