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Date:   Sat, 18 May 2019 06:42:14 -0700
From:   Doug Anderson <dianders@...omium.org>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     Guenter Roeck <groeck@...omium.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Elaine Zhang <zhangqing@...k-chips.com>,
        Caesar <wxt@...k-chips.com>, Lin Huang <hl@...k-chips.com>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
        Derek Basehore <dbasehore@...omium.org>,
        Matthias Kaehlcke <mka@...omium.org>,
        Ryan Case <ryandcase@...omium.org>
Subject: Re: [PATCH] phy: rockchip-dp: Avoid power leak by leaving the PHY
 power on

Hi,

On Sat, May 18, 2019 at 12:51 AM Heiko Stuebner <heiko@...ech.de> wrote:
>
> Hi,
>
> Am Samstag, 18. Mai 2019, 01:57:47 CEST schrieb Doug Anderson:
> > Elaine and Caesar,
> >
> > On Tue, May 7, 2019 at 4:50 PM Douglas Anderson <dianders@...omium.org> wrote:
> > >
> > > While testing a newer kernel on rk3288-based Chromebooks I found that
> > > the power draw in suspend was higher on newer kernels compared to the
> > > downstream Chrome OS 3.14 kernel.  Specifically the power of an
> > > rk3288-veyron-jerry board that I tested (as measured by the smart
> > > battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.
> > >
> > > I tracked the regression down to the fact that the "DP PHY" driver
> > > didn't exist in our downstream 3.14.  We relied on the eDP driver to
> > > turn on the clock and relied on the fact that the power for the PHY
> > > was default turned on.
> > >
> > > Specifically the thing that caused the power regression was turning
> > > the eDP PHY _off_.  Presumably there is some sort of power leak in the
> > > system and when we turn the PHY off something is leaching power from
> > > something else and causing excessive power draw.
> > >
> > > Doing a search through device trees shows that this PHY is only ever
> > > used on rk3288.  Presumably this power leak is present on all
> > > rk3288-SoCs running upstream Linux so let's just whack the driver to
> > > make sure we never turn off power.  We'll still leave the parts that
> > > turn _on_ the power and grab the clock, though.
> > >
> > > NOTES:
> > > A) If someone can identify what this power leak is and fix it in some
> > >    other way we can revert this patch.
> > > B) If someone can show that their particular board doesn't have this
> > >    power leak (maybe they have rails hooked up differently?) we can
> > >    perhaps add a device tree property indicating that for some boards
> > >    it's OK to turn this rail off.  I don't want to add this property
> > >    until I know of a board that needs it.
> > >
> > > Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
> > > Signed-off-by: Douglas Anderson <dianders@...omium.org>
> > > ---
> > > As far as I know Yakir (the original author) is no longer at Rockchip.
> > > I've added a few other Rockchip people and hopefully one of them can
> > > help direct even if they're not directly responsible.
> > >
> > >  drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
> > >  1 file changed, 7 insertions(+), 4 deletions(-)
> >
> > Can you help direct this to the right person?  ...or should we just
> > land it and assume it's fine?
>
> I tink Kishon as phy-maintainer is the correct person to take on this
> patch, but maybe he's waiting for the merge-window to be over.

Yeah, definitely Kishon should be the one to land.  I was kinda hoping
to get confirmation from the Rockchip guys that this was a good idea
across the board for rk3288 since I can only really test
rk3288-veyron.  They'd have access to the SoC design and could tell
more about what this bit actually does in the SoC.

...in any case, if they don't respond then presumably we'd be good to
land once the merge window is over and Kishon is landing patches
again.

-Doug

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