linux-kernel - Re: [PATCH] tty: serial: msm

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 20 May 2019 08:11:01 -0700
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Jorge Ramirez <jorge.ramirez-ortiz@...aro.org>
Cc:     Stephen Boyd <sboyd@...nel.org>, agross@...nel.org,
        david.brown@...aro.org, gregkh@...uxfoundation.org,
        jslaby@...e.com, keescook@...omium.org, anton@...msg.org,
        ccross@...roid.com, tony.luck@...el.com,
        linux-arm-msm@...r.kernel.org, linux-serial@...r.kernel.org,
        linux-kernel@...r.kernel.org, khasim.mohammed@...aro.org,
        agsumit@....qualcomm.com
Subject: Re: [PATCH] tty: serial: msm_serial: Fix XON/XOFF

On Mon 20 May 07:58 PDT 2019, Jorge Ramirez wrote:

> On 5/20/19 16:56, Jorge Ramirez wrote:
> > On 5/20/19 16:51, Stephen Boyd wrote:
> >> Quoting Jorge Ramirez-Ortiz (2019-05-20 03:34:35)
> >>> When the tty layer requests the uart to throttle, the current code
> >>> executing in msm_serial will trigger "Bad mode in Error Handler" and
> >>> generate an invalid stack frame in pstore before rebooting (that is if
> >>> pstore is indeed configured: otherwise the user shall just notice a
> >>> reboot with no further information dumped to the console).
> >>>
> >>> This patch replaces the PIO byte accessor with the word accessor
> >>> already used in PIO mode.
> >>
> >> Because the hardware only accepts word based accessors and fails
> >> otherwise? I can believe that.
> >>
> >> I wonder if the earlier UART hardware this driver used to support (i.e.
> >> pre-DM) would accept byte access to the registers. It's possible, but we
> >> don't really care because those boards aren't supported.
> > 
> > ok.
> > 
> > also the PIO path uses iowrite32_rep to write a number of bytes (from 1
> > to 4) so I think it is also appropriate to use it for XON/XOFF.
> > 
> >>
> >>>
> >>> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>
> >>> ---
> >>
> >> Reviewed-by: Stephen Boyd <swboyd@...omium.org>
> >>
> >>>  drivers/tty/serial/msm_serial.c | 5 ++++-
> >>>  1 file changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
> >>> index 109096033bb1..23833ad952ba 100644
> >>> --- a/drivers/tty/serial/msm_serial.c
> >>> +++ b/drivers/tty/serial/msm_serial.c
> >>> @@ -869,10 +870,12 @@ static void msm_handle_tx(struct uart_port *port)
> >>>                 else
> >>>                         tf = port->membase + UART_TF;
> >>>  
> >>> +               buf[0] = port->x_char;
> >>> +
> >>>                 if (msm_port->is_uartdm)
> >>>                         msm_reset_dm_count(port, 1);
> >>>  
> >>> -               iowrite8_rep(tf, &port->x_char, 1);
> >>> +               iowrite32_rep(tf, buf, 1);
> >>
> >> I suppose it's OK to write some extra zeroes here?
> >>
> >>
> > 
> > yeah, semantically confusing msm_reset_dm_count is what really matters:
> > it tells the hardware to only take n bytes (in this case only one) so
> > the others will be ignored
> 
> um after I said this, maybe iowrite32_rep should only be applied to
> uartdm ... what do you think?
> 

If I read the history correctly this write was a writel() up until
68252424a7c7 ("tty: serial: msm: Support big-endian CPUs").

So I think you should just change this back to a iowrite32_rep() and add
a Fixes tag.

Regards,
Bjorn