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Date:   Mon, 20 May 2019 08:12:06 +0000
From:   Xiaowei Bao <xiaowei.bao@....com>
To:     Arnd Bergmann <arnd@...db.de>
CC:     Bjorn Helgaas <bhelgaas@...gle.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Shawn Guo <shawnguo@...nel.org>, Leo Li <leoyang.li@....com>,
        Kishon <kishon@...com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        gregkh <gregkh@...uxfoundation.org>,
        "M.h. Lian" <minghuan.lian@....com>,
        Mingkai Hu <mingkai.hu@....com>, Roy Zang <roy.zang@....com>,
        Kate Stewart <kstewart@...uxfoundation.org>,
        Philippe Ombredanne <pombredanne@...b.com>,
        Shawn Lin <shawn.lin@...k-chips.com>,
        linux-pci <linux-pci@...r.kernel.org>,
        DTML <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        linuxppc-dev <linuxppc-dev@...ts.ozlabs.org>
Subject: RE: [EXT] Re: [PATCH 2/3] arm64: dts: ls1028a: Add PCIe controller DT
 nodes

Hi Arndt,

-----Original Message-----
From: Arnd Bergmann <arnd@...db.de> 
Sent: 2019年5月17日 16:59
To: Xiaowei Bao <xiaowei.bao@....com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>; Rob Herring <robh+dt@...nel.org>; Mark Rutland <mark.rutland@....com>; Shawn Guo <shawnguo@...nel.org>; Leo Li <leoyang.li@....com>; Kishon <kishon@...com>; Lorenzo Pieralisi <lorenzo.pieralisi@....com>; gregkh <gregkh@...uxfoundation.org>; M.h. Lian <minghuan.lian@....com>; Mingkai Hu <mingkai.hu@....com>; Roy Zang <roy.zang@....com>; Kate Stewart <kstewart@...uxfoundation.org>; Philippe Ombredanne <pombredanne@...b.com>; Shawn Lin <shawn.lin@...k-chips.com>; linux-pci <linux-pci@...r.kernel.org>; DTML <devicetree@...r.kernel.org>; Linux Kernel Mailing List <linux-kernel@...r.kernel.org>; Linux ARM <linux-arm-kernel@...ts.infradead.org>; linuxppc-dev <linuxppc-dev@...ts.ozlabs.org>
Subject: Re: [EXT] Re: [PATCH 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes

Caution: EXT Email

On Fri, May 17, 2019 at 5:21 AM Xiaowei Bao <xiaowei.bao@....com> wrote:
> -----Original Message-----
> From: Arnd Bergmann <arnd@...db.de>
> On Wed, May 15, 2019 at 9:36 AM Xiaowei Bao <xiaowei.bao@....com> wrote:
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |   52 ++++++++++++++++++++++++
> >  1 files changed, 52 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index b045812..50b579b 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -398,6 +398,58 @@
> >                         status = "disabled";
> >                 };
> >
> > +               pcie@...0000 {
> > +                       compatible = "fsl,ls1028a-pcie";
> > +                       reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
> > +                              0x80 0x00000000 0x0 0x00002000>; /* configuration space */
> > +                       reg-names = "regs", "config";
> > +                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > +                                    <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> > +                       interrupt-names = "pme", "aer";
> > +                       #address-cells = <3>;
> > +                       #size-cells = <2>;
> > +                       device_type = "pci";
> > +                       dma-coherent;
> > +                       num-lanes = <4>;
> > +                       bus-range = <0x0 0xff>;
> > +                       ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */
> > +                                 0x82000000 0x0 0x40000000 0x80 
> > + 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
>
> Are you sure there is no support for 64-bit BARs or prefetchable memory?
> [Xiaowei Bao] sorry for late reply, Thought that our Layerscape platform has not added prefetchable memory support in DTS, so this platform has not been added, I will submit a separate patch to add prefetchable memory support for all Layerscape platforms.

Ok, thanks.

> Of course, the prefetchable PCIE device can work in our boards, 
> because the RC will assign non-prefetchable memory for this device. We 
> reserve 1G no-prefetchable memory for PCIE device, it is enough for general devices.

Sure, many devices work just fine, this is mostly a question of supporting those devices that do require multiple gigabytes, or that need prefetchable memory semantics to get the expected performance. GPUs are the obvious example, but I think there are others (infiniband?).
[Xiaowei Bao] sorry, I don't know much about infiniband and GPU, as you said, I think many devices works fine with this DTS, I will add the prefetchable memory entry in DTS future and submit another patch.

      Arnd

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